ARM32 instructions (Thumb-2)

Instruction reference: i386 · x64 · ARM32 (Thumb-2) · ARM64 (AArch64)

154 instructions in 231 forms for .arch thumb: name, operands, the bit encoding (16 or 32 bits) and a short description with the operation in pseudo code. Included are the 16-bit instructions and the 32-bit instructions: arithmetic, logic, shifts, bitfields, multiplication and division, loads and stores (also unprivileged and exclusive), branches, system instructions, coprocessor access and floating point (VFP). Every instruction that Dismonite decodes is included. Not included yet are NEON, the DSP and saturating instructions and further variants. The classic ARM mode (A32) is missing because Windows on ARM uses only Thumb-2.

How to read the table

A Thumb instruction is 16 or 32 bits long; a 32-bit instruction consists of two half words that follow each other in memory (the upper half word first, here on the left, then the lower one, here on the right, with a gap between). The encoding shows the bits from left (highest bit number) to right: fixed bits as digits (the opcode), the names are fields. Hover a field to see its range of bits. Rd, Rn, Rm, Rt are registers: mostly 3 bits (r0 to r7) in 16-bit instructions, 4 bits (r0 to r15) in 32-bit ones. imm… is a constant, cond a condition (4 bits), S chooses the form that sets the flags. Below is the value of the fixed bits and the mask in hex: an instruction belongs to this form if (word & mask) == value.

Flags: The 16-bit arithmetic instructions set the flags (N Z C V) when they are not in an IT block, and otherwise not; hence the names adds, movs, lsls ... The 32-bit forms set the flags only if the bit S is set. Operation: Rd = Rn + Rm and the like is pseudo code; sext and zext extend with sign and with zeros, >>s shifts with sign, [x] is the memory at address x.

Every encoding in this table is checked against the decoder of Dismonite: with random values in the fields it gives this instruction (or its alias) again.

Instruction	Operands	Encoding	Description
adc	Rd, Rn, #const	11110 i 0 1010 S Rn 0 imm3 Rd imm80xF1400000 / mask 0xFBE08000	Addition with carry: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn + const + C; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Arithmetic
adc	Rd, Rn, Rm{, shift #imm}	1110101 1010 S Rn 0 imm3 Rd imm2 type Rm0xEB400000 / mask 0xFFE08000	Addition with carry: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn + shift(Rm) + C`Flags: N Z C V (if S)Arithmetic
adcs	Rdn, Rmalso shown as: adc	010000 0101 Rm Rdn0x4140 / mask 0xFFC0	Addition with carry (C)`Rdn = Rdn + Rm + C`Flags: N Z C VArithmetic
add	Rdn, Rm	010001 00 DN Rm Rdn0x4400 / mask 0xFF00	Addition of two registers (also r8 to r15, sets no flags)`Rdn = Rdn + Rm`Arithmetic
	Rd, sp, #imm8*4	1010 1 Rd imm80xA800 / mask 0xF800	Addition of the stack pointer and a constant`Rd = sp + imm8 * 4`Arithmetic
	sp, sp, #imm7*4	1011 0000 0 imm70xB000 / mask 0xFF80	Increase of the stack pointer`sp = sp + imm7 * 4`Arithmetic
	Rd, Rn, #constalso shown as: cmn	11110 i 0 1000 S Rn 0 imm3 Rd imm80xF1000000 / mask 0xFBE08000	Addition: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn + const; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Arithmetic
	Rd, Rn, Rm{, shift #imm}also shown as: cmn	1110101 1000 S Rn 0 imm3 Rd imm2 type Rm0xEB000000 / mask 0xFFE08000	Addition: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn + shift(Rm)`Flags: N Z C V (if S)Arithmetic
adds	Rd, Rn, Rmalso shown as: add	000 11 0 0 Rm Rn Rd0x1800 / mask 0xFE00	Addition of two registers`Rd = Rn + Rm`Flags: N Z C VArithmetic
	Rd, Rn, #imm3also shown as: add	000 11 1 0 imm3 Rn Rd0x1C00 / mask 0xFE00	Addition of a constant (3 bit)`Rd = Rn + imm3`Flags: N Z C VArithmetic
	Rdn, #imm8also shown as: add	001 10 Rdn imm80x3000 / mask 0xF800	Addition of a constant (8 bit)`Rdn = Rdn + imm8`Flags: N Z C VArithmetic
addw	Rd, Rn, #imm12also shown as: add	11110 i 100000 Rn 0 imm3 Rd imm80xF2000000 / mask 0xFBF08000	Addition of a constant (12 bit)`Rd = Rn + imm12 (i:imm3:imm8)`Arithmetic
adr	Rd, labelalso shown as: add	1010 0 Rd imm80xA000 / mask 0xF800	Address relative to the program counter`Rd = align(pc, 4) + imm8 * 4`Constants and addresses
and	Rd, Rn, #constalso shown as: tst	11110 i 0 0000 S Rn 0 imm3 Rd imm80xF0000000 / mask 0xFBE08000	Bitwise AND: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn & const; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Logic and bits
and	Rd, Rn, Rm{, shift #imm}also shown as: tst	1110101 0000 S Rn 0 imm3 Rd imm2 type Rm0xEA000000 / mask 0xFFE08000	Bitwise AND: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn & shift(Rm)`Flags: N Z C V (if S)Logic and bits
ands	Rdn, Rmalso shown as: and	010000 0000 Rm Rdn0x4000 / mask 0xFFC0	Bitwise AND`Rdn = Rdn & Rm`Flags: N ZLogic and bits
asr	Rd, Rn, Rm	11111010 0 10 S Rn 1111 Rd 0000 Rm0xFA40F000 / mask 0xFFE0F0F0	Shift right signed by a register (32-bit form)`Rd = Rn >>s Rm[7:0]`Flags: N Z C (if S)Shift and rotate
asrs	Rd, Rm, #imm5also shown as: asr	000 10 imm5 Rm Rd0x1000 / mask 0xF800	Shift right signed by a constant`Rd = Rm >>s imm5 (imm5 = 0 means 32)`Flags: N Z CShift and rotate
asrs	Rdn, Rmalso shown as: asr	010000 0100 Rm Rdn0x4100 / mask 0xFFC0	Shift right signed by a register`Rdn = Rdn >>s Rm[7:0]`Flags: N Z CShift and rotate
b	label	11100 imm110xE000 / mask 0xF800	Jump (relative, +-2 KB)`pc = pc + (sext(imm11) << 1)`Branches and calls
b	label	11110 S imm10 10 J1 1 J2 imm110xF0009000 / mask 0xF800D000	Jump (relative, +-16 MB)`pc = pc + sext(S:J1:J2:imm10:imm11 << 1)`Branches and calls
b.cond	label	1101 cond imm80xD000 / mask 0xF000	Conditional jump (relative, +-256 bytes)`if cond then pc = pc + (sext(imm8) << 1)`Branches and calls
b.cond	label	11110 S cond imm6 10 J1 0 J2 imm110xF0008000 / mask 0xF800D000	Conditional jump (relative, +-1 MB)`if cond then pc = pc + sext(S:J2:J1:imm6:imm11 << 1)`Branches and calls
bfi	Rd, Rn, #lsb, #widthalso shown as: bfc	11110 0 110110 Rn 0 imm3 Rd imm2 0 msb0xF3600000 / mask 0xFFF08020	Insertion of a bitfield from Rn into Rd (bfc: zeros)`Rd[msb : lsb] = Rn[msb - lsb : 0]`Bitfields
bic	Rd, Rn, #const	11110 i 0 0001 S Rn 0 imm3 Rd imm80xF0200000 / mask 0xFBE08000	Bitwise AND with an inverted constant: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn & ~const; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Logic and bits
bic	Rd, Rn, Rm{, shift #imm}	1110101 0001 S Rn 0 imm3 Rd imm2 type Rm0xEA200000 / mask 0xFFE08000	Bitwise AND with an inverted operand: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn & ~shift(Rm)`Flags: N Z C V (if S)Logic and bits
bics	Rdn, Rmalso shown as: bic	010000 1110 Rm Rdn0x4380 / mask 0xFFC0	Bitwise AND with an inverted operand (bit clear)`Rdn = Rdn & ~Rm`Flags: N ZLogic and bits
bkpt	#imm8	1011 1110 imm80xBE00 / mask 0xFF00	Breakpoint`raise a breakpoint exception`System and privileged
bl	label	11110 S imm10 11 J1 1 J2 imm110xF000D000 / mask 0xF800D000	Call of a function (relative, +-16 MB, lr = return address)`lr = (pc + 4) \| 1; pc = pc + sext(S:J1:J2:imm10:imm11 << 1)`Branches and calls
blx	Rm	010001 11 1 Rm 0000x4780 / mask 0xFF87	Call of the function at the address in the register (lr = return address)`lr = (pc + 2) \| 1; pc = Rm & ~1`Branches and calls
blx	label	11110 S imm10 11 J1 0 J2 imm10 00xF000C000 / mask 0xF800D001	Call of an ARM function (relative, switches to the ARM instruction set)`lr = (pc + 4) \| 1; pc = align(pc, 4) + sext(S:J1:J2:imm10H:imm10L << 2); instruction set = ARM`Branches and calls
blxns	Rm	010001111 Rm 1000x4784 / mask 0xFF87	Call of a register with a change to the non-secure state (TrustZone, ARMv8-M)`lr = next; pc = Rm; state = non-secure`Branches and calls
bx	Rm	010001 11 0 Rm 0000x4700 / mask 0xFF87	Jump to the address in the register (bit 0 selects Thumb, ARM if bit 0 = 0)`pc = Rm & ~1; instruction set = Rm[0]`Branches and calls
bxns	Rm	010001110 Rm 1000x4704 / mask 0xFF87	Jump to a register with a change to the non-secure state (TrustZone, ARMv8-M)`pc = Rm; state = non-secure`Branches and calls
cbnz	Rn, label	1011 10 i 1 imm5 Rn0xB900 / mask 0xFD00	Jump forward if the register is not 0`if Rn != 0 then pc = pc + (i:imm5 << 1)`Branches and calls
cbz	Rn, label	1011 00 i 1 imm5 Rn0xB100 / mask 0xFD00	Jump forward if the register is 0`if Rn == 0 then pc = pc + (i:imm5 << 1)`Branches and calls
clz	Rd, Rm	111110101011 Rm 1111 Rd 1000 Rm0xFAB0F080 / mask 0xFFF0F0F0	Count of the leading zero bits`Rd = count_leading_zeros(Rm)`Logic and bits
cmn	Rn, Rm	010000 1011 Rm Rn0x42C0 / mask 0xFFC0	Comparison by addition (Rn plus Rm), only the flags change`flags = Rn + Rm`Flags: N Z C VCompare and exchange
cmp	Rn, #imm8	001 01 Rn imm80x2800 / mask 0xF800	Comparison with a constant (8 bit)`flags = Rn - imm8`Flags: N Z C VCompare and exchange
	Rn, Rm	010000 1010 Rm Rn0x4280 / mask 0xFFC0	Comparison (Rn minus Rm), only the flags change`flags = Rn - Rm`Flags: N Z C VCompare and exchange
	Rn, Rm	010001 01 N Rm Rn0x4500 / mask 0xFF00	Comparison of two registers (also r8 to r15)`flags = Rn - Rm`Flags: N Z C VCompare and exchange
cpsid	ialso shown as: cpsie	1011 0110 011 im 0 0 1 00xB662 / mask 0xFFEF	Disabling (cpsid) or enabling (cpsie) of interrupts (privileged)`PRIMASK = im`System and privileged
dmb	option	111100111011 1111 1000 1111 0101 option0xF3BF8F50 / mask 0xFFFFFFF0	Memory barrier for the order of the accesses`earlier memory accesses are observed before later ones`System and privileged
dsb	option	111100111011 1111 1000 1111 0100 option0xF3BF8F40 / mask 0xFFFFFFF0	Memory barrier: waits until all accesses are complete`wait until all earlier memory accesses are complete`System and privileged
eor	Rd, Rn, #constalso shown as: teq	11110 i 0 0100 S Rn 0 imm3 Rd imm80xF0800000 / mask 0xFBE08000	Bitwise exclusive OR: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn ^ const; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Logic and bits
eor	Rd, Rn, Rm{, shift #imm}also shown as: teq	1110101 0100 S Rn 0 imm3 Rd imm2 type Rm0xEA800000 / mask 0xFFE08000	Bitwise exclusive OR: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn ^ shift(Rm)`Flags: N Z C V (if S)Logic and bits
eors	Rdn, Rmalso shown as: eor	010000 0001 Rm Rdn0x4040 / mask 0xFFC0	Bitwise exclusive OR`Rdn = Rdn ^ Rm`Flags: N ZLogic and bits
hint	#imm	10111111 hint 00000xBF00 / mask 0xFF0F	Hint instruction with a number from 0 to 15 (nop, yield, wfe, wfi, sev have their own names; the others do nothing)`no change`System and privileged
isb	option	111100111011 1111 1000 1111 0110 option0xF3BF8F60 / mask 0xFFFFFFF0	Instruction barrier: flushes the pipeline`all instructions after it are fetched anew`System and privileged
it	{x{y{z}}} condalso shown as: ite, itt, itee, itet, itte, ittt, iteee, iteet, itete, itett, ittee, ittet, ittte, itttt	1011 1111 firstcond mask0xBF00 / mask 0xFF00	IT block: makes the following 1 to 4 instructions conditional`the next instructions run only if the condition holds (or its opposite for else)`System and privileged
ldm	Rn{!}, {registers}also shown as: ldmia	11001 Rn register_list0xC800 / mask 0xF800	Load of several registers (increasing)`for each register in the list: reg = [Rn]; Rn = Rn + 4`Loads and stores
ldm	Rn{!}, {registers}also shown as: ldmia, pop	1110100010 W 1 Rn register_list0xE8900000 / mask 0xFFD00000	Load of several registers (increasing)`for each register in the list: reg = [Rn]; Rn = Rn + 4`Loads and stores
ldmdb	Rn{!}, {registers}	1110100100 W 1 Rn register_list0xE9100000 / mask 0xFFD00000	Load of several registers (decreasing)`for each register in the list, last first: Rn = Rn - 4; reg = [Rn]`Loads and stores
ldr	Rt, label	01001 Rt imm80x4800 / mask 0xF800	Load of a word relative to the program counter (literal pool, up to 1020 bytes)`Rt = [align(pc, 4) + imm8 * 4]`Loads and stores
	Rt, [Rn, Rm]	0101 100 Rm Rn Rt0x5800 / mask 0xFE00	Load of a word (register address)`Rt = [Rn + Rm]`Loads and stores
	Rt, [Rn{, #imm5*4}]	011 01 imm5 Rn Rt0x6800 / mask 0xF800	Load of a word (constant offset)`Rt = [Rn + imm5 * 4]`Loads and stores
	Rt, [sp{, #imm8*4}]	100 11 Rt imm80x9800 / mask 0xF800	Load of a word relative to the stack pointer`Rt = [sp + imm8 * 4]`Loads and stores
	Rt, [Rn, #imm12]	111110001101 Rn Rt imm120xF8D00000 / mask 0xFFF00000	Load of a word (constant, 12 bit, forward only)`Rt = [Rn + imm12]`Loads and stores
	Rt, [Rn, #+/-imm8]{!} / [Rn], #+/-imm8	111110000101 Rn Rt 1 P U W imm80xF8500800 / mask 0xFFF00800	Load of a word (constant, 8 bit, with or without write-back)`Rt = [Rn +/- imm8]`Loads and stores
	Rt, [Rn, Rm{, lsl #imm2}]	111110000101 Rn Rt 000000 imm2 Rm0xF8500000 / mask 0xFFF00FC0	Load of a word (register, optionally shifted left by 0 to 3)`Rt = [Rn + (Rm << imm2)]`Loads and stores
	Rt, label	11111000 U 1011111 Rt imm120xF85F0000 / mask 0xFF7F0000	Load of a word relative to the program counter (+-4 KB)`Rt = [align(pc, 4) +/- imm12]`Loads and stores
ldrb	Rt, [Rn, Rm]	0101 110 Rm Rn Rt0x5C00 / mask 0xFE00	Load of a byte (register address)`Rt = zext([Rn + Rm])`Loads and stores
	Rt, [Rn{, #imm5}]	011 11 imm5 Rn Rt0x7800 / mask 0xF800	Load of a byte (constant offset)`Rt = zext([Rn + imm5])`Loads and stores
	Rt, [Rn, #imm12]	111110001001 Rn Rt imm120xF8900000 / mask 0xFFF00000	Load of a byte (constant, 12 bit, forward only)`Rt = zext([Rn + imm12])`Loads and stores
	Rt, [Rn, #+/-imm8]{!} / [Rn], #+/-imm8	111110000001 Rn Rt 1 P U W imm80xF8100800 / mask 0xFFF00800	Load of a byte (constant, 8 bit, with or without write-back)`Rt = zext([Rn +/- imm8])`Loads and stores
	Rt, [Rn, Rm{, lsl #imm2}]	111110000001 Rn Rt 000000 imm2 Rm0xF8100000 / mask 0xFFF00FC0	Load of a byte (register, optionally shifted left by 0 to 3)`Rt = zext([Rn + (Rm << imm2)])`Loads and stores
ldrbt	Rt, [Rn{, #imm8}]	111110000001 Rn Rt 1110 imm80xF8100E00 / mask 0xFFF00F00	Load of a byte with the rights of user mode`Rt = zext([Rn + imm8])`Loads and stores
ldrd	Rt, Rt2, [Rn, #+/-imm84]{!} / [Rn], #+/-imm84	1110100 P U 1 W 1 Rn Rt Rt2 imm80xE8500000 / mask 0xFE500000	Load of a register pair (two words)`Rt = [addr]; Rt2 = [addr + 4]`Loads and stores
ldrex	Rt, [Rn{, #imm8*4}]	111010000101 Rn Rt 1111 imm80xE8500F00 / mask 0xFFF00F00	Load-exclusive: sets the exclusive monitor`Rt = [Rn + imm8 * 4]; set the exclusive monitor`Loads and stores
ldrexb	Rt, [Rn]	111010001101 Rn Rt 1111 0100 11110xE8D00F4F / mask 0xFFF00FFF	Load of a byte (exclusive)`Rt = zext([Rn]); set the exclusive monitor`Loads and stores
ldrexd	Rt, Rt2, [Rn]	111010001101 Rn Rt Rt2 0111 11110xE8D0007F / mask 0xFFF000FF	Load of a double word (exclusive): sets the exclusive monitor`Rt:Rt2 = [Rn]; mark exclusive`Loads and stores
ldrexh	Rt, [Rn]	111010001101 Rn Rt 1111 0101 11110xE8D00F5F / mask 0xFFF00FFF	Load of a half word (exclusive)`Rt = zext([Rn]); set the exclusive monitor`Loads and stores
ldrh	Rt, [Rn, Rm]	0101 101 Rm Rn Rt0x5A00 / mask 0xFE00	Load of a half word (register address)`Rt = zext([Rn + Rm])`Loads and stores
	Rt, [Rn{, #imm5*2}]	100 01 imm5 Rn Rt0x8800 / mask 0xF800	Load of a half word (constant offset)`Rt = zext([Rn + imm5 * 2])`Loads and stores
	Rt, [Rn, #imm12]	111110001011 Rn Rt imm120xF8B00000 / mask 0xFFF00000	Load of a half word (constant, 12 bit, forward only)`Rt = zext([Rn + imm12])`Loads and stores
	Rt, [Rn, #+/-imm8]{!} / [Rn], #+/-imm8	111110000011 Rn Rt 1 P U W imm80xF8300800 / mask 0xFFF00800	Load of a half word (constant, 8 bit, with or without write-back)`Rt = zext([Rn +/- imm8])`Loads and stores
	Rt, [Rn, Rm{, lsl #imm2}]	111110000011 Rn Rt 000000 imm2 Rm0xF8300000 / mask 0xFFF00FC0	Load of a half word (register, optionally shifted left by 0 to 3)`Rt = zext([Rn + (Rm << imm2)])`Loads and stores
ldrht	Rt, [Rn{, #imm8}]	111110000011 Rn Rt 1110 imm80xF8300E00 / mask 0xFFF00F00	Load of a half word with the rights of user mode`Rt = zext([Rn + imm8])`Loads and stores
ldrsb	Rt, [Rn, Rm]	0101 011 Rm Rn Rt0x5600 / mask 0xFE00	Load of a signed byte (register address)`Rt = sext([Rn + Rm])`Loads and stores
	Rt, [Rn, #imm12]	111110011001 Rn Rt imm120xF9900000 / mask 0xFFF00000	Load of a signed byte (constant, 12 bit, forward only)`Rt = sext([Rn + imm12])`Loads and stores
	Rt, [Rn, #+/-imm8]{!} / [Rn], #+/-imm8	111110010001 Rn Rt 1 P U W imm80xF9100800 / mask 0xFFF00800	Load of a signed byte (constant, 8 bit, with or without write-back)`Rt = sext([Rn +/- imm8])`Loads and stores
	Rt, [Rn, Rm{, lsl #imm2}]	111110010001 Rn Rt 000000 imm2 Rm0xF9100000 / mask 0xFFF00FC0	Load of a signed byte (register, optionally shifted left by 0 to 3)`Rt = sext([Rn + (Rm << imm2)])`Loads and stores
ldrsbt	Rt, [Rn{, #imm8}]	111110010001 Rn Rt 1110 imm80xF9100E00 / mask 0xFFF00F00	Load of a byte with sign extension with the rights of user mode`Rt = sext([Rn + imm8])`Loads and stores
ldrsh	Rt, [Rn, Rm]	0101 111 Rm Rn Rt0x5E00 / mask 0xFE00	Load of a signed half word (register address)`Rt = sext([Rn + Rm])`Loads and stores
	Rt, [Rn, #imm12]	111110011011 Rn Rt imm120xF9B00000 / mask 0xFFF00000	Load of a signed half word (constant, 12 bit, forward only)`Rt = sext([Rn + imm12])`Loads and stores
	Rt, [Rn, #+/-imm8]{!} / [Rn], #+/-imm8	111110010011 Rn Rt 1 P U W imm80xF9300800 / mask 0xFFF00800	Load of a signed half word (constant, 8 bit, with or without write-back)`Rt = sext([Rn +/- imm8])`Loads and stores
	Rt, [Rn, Rm{, lsl #imm2}]	111110010011 Rn Rt 000000 imm2 Rm0xF9300000 / mask 0xFFF00FC0	Load of a signed half word (register, optionally shifted left by 0 to 3)`Rt = sext([Rn + (Rm << imm2)])`Loads and stores
ldrsht	Rt, [Rn{, #imm8}]	111110010011 Rn Rt 1110 imm80xF9300E00 / mask 0xFFF00F00	Load of a half word with sign extension with the rights of user mode`Rt = sext([Rn + imm8])`Loads and stores
ldrt	Rt, [Rn{, #imm8}]	111110000101 Rn Rt 1110 imm80xF8500E00 / mask 0xFFF00F00	Load of a word with the rights of user mode`Rt = [Rn + imm8]`Loads and stores
lsl	Rd, Rn, Rm	11111010 0 00 S Rn 1111 Rd 0000 Rm0xFA00F000 / mask 0xFFE0F0F0	Shift left by a register (32-bit form)`Rd = Rn << Rm[7:0]`Flags: N Z C (if S)Shift and rotate
lsls	Rd, Rm, #imm5also shown as: lsl, movs	000 00 imm5 Rm Rd0x0000 / mask 0xF800	Shift left by a constant`Rd = Rm << imm5`Flags: N Z CShift and rotate
lsls	Rdn, Rmalso shown as: lsl	010000 0010 Rm Rdn0x4080 / mask 0xFFC0	Shift left by a register`Rdn = Rdn << Rm[7:0]`Flags: N Z CShift and rotate
lsr	Rd, Rn, Rm	11111010 0 01 S Rn 1111 Rd 0000 Rm0xFA20F000 / mask 0xFFE0F0F0	Shift right unsigned by a register (32-bit form)`Rd = Rn >> Rm[7:0]`Flags: N Z C (if S)Shift and rotate
lsrs	Rd, Rm, #imm5also shown as: lsr	000 01 imm5 Rm Rd0x0800 / mask 0xF800	Shift right unsigned by a constant`Rd = Rm >> imm5 (imm5 = 0 means 32)`Flags: N Z CShift and rotate
lsrs	Rdn, Rmalso shown as: lsr	010000 0011 Rm Rdn0x40C0 / mask 0xFFC0	Shift right unsigned by a register`Rdn = Rdn >> Rm[7:0]`Flags: N Z CShift and rotate
mcr	coproc, #opc1, Rt, CRn, CRm{, #opc2}also shown as: mrc	1110 1110 opc1 L CRn Rt coproc opc2 1 CRm0xEE000010 / mask 0xFF000010	Coprocessor access: write of a register to a coprocessor (mcr) or read (mrc, L = 1)`coprocessor register = Rt or Rt = coprocessor register`System and privileged
mla	Rd, Rn, Rm, Ra	111110110000 Rn Ra Rd 0000 Rm0xFB000000 / mask 0xFFF000F0	Multiply and add`Rd = Ra + Rn * Rm`Arithmetic
mls	Rd, Rn, Rm, Ra	111110110000 Rn Ra Rd 0001 Rm0xFB000010 / mask 0xFFF000F0	Multiply and subtract`Rd = Ra - Rn * Rm`Arithmetic
mov	Rd, Rm	010001 10 D Rm Rd0x4600 / mask 0xFF00	Copy of a register (also r8 to r15, sets no flags)`Rd = Rm`Constants and addresses
movs	Rd, #imm8also shown as: mov	001 00 Rd imm80x2000 / mask 0xF800	Load of a constant (8 bit)`Rd = imm8`Flags: N ZConstants and addresses
movt	Rd, #imm16	11110 i 101100 imm4 0 imm3 Rd imm80xF2C00000 / mask 0xFBF08000	Load of the upper half of a register (the lower half stays)`Rd[31:16] = imm4:i:imm3:imm8`Constants and addresses
movw	Rd, #imm16also shown as: mov	11110 i 100100 imm4 0 imm3 Rd imm80xF2400000 / mask 0xFBF08000	Load of a 16-bit constant (the upper half 0)`Rd = zext(imm4:i:imm3:imm8)`Constants and addresses
mrs	Rd, sysreg	1111001111101111 1000 Rd SYSm0xF3EF8000 / mask 0xFFFFF000	Read of a system register (apsr, ipsr, msp, psp, primask ...)`Rd = sysreg`System and privileged
msr	sysreg, Rn	111100111000 Rn 1000 mask 00 SYSm0xF3808000 / mask 0xFFF0F300	Write of a system register`sysreg = Rn`System and privileged
mul	Rd, Rn, Rm	111110110000 Rn 1111 Rd 0000 Rm0xFB00F000 / mask 0xFFF0F0F0	Multiplication (low 32 bits)`Rd = Rn * Rm`Arithmetic
muls	Rdm, Rn, Rdmalso shown as: mul	010000 1101 Rn Rdm0x4340 / mask 0xFFC0	Multiplication (low 32 bits)`Rdm = Rn * Rdm`Flags: N ZArithmetic
mvns	Rd, Rmalso shown as: mvn	010000 1111 Rm Rd0x43C0 / mask 0xFFC0	Bitwise inversion`Rd = ~Rm`Flags: N ZLogic and bits
nop		1011 1111 0000 00000xBF00 / mask 0xFFFF	No operation`no change`System and privileged
orn	Rd, Rn, #constalso shown as: mvn	11110 i 0 0011 S Rn 0 imm3 Rd imm80xF0600000 / mask 0xFBE08000	Bitwise OR with an inverted constant: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn OR ~const; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Logic and bits
orn	Rd, Rn, Rm{, shift #imm}also shown as: mvn	1110101 0011 S Rn 0 imm3 Rd imm2 type Rm0xEA600000 / mask 0xFFE08000	Bitwise OR with an inverted operand: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn OR ~shift(Rm)`Flags: N Z C V (if S)Logic and bits
orr	Rd, Rn, #constalso shown as: mov	11110 i 0 0010 S Rn 0 imm3 Rd imm80xF0400000 / mask 0xFBE08000	Bitwise OR: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn OR const; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Logic and bits
orr	Rd, Rn, Rm{, shift #imm}also shown as: mov, lsl, lsr, asr, ror	1110101 0010 S Rn 0 imm3 Rd imm2 type Rm0xEA400000 / mask 0xFFE08000	Bitwise OR: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn OR shift(Rm)`Flags: N Z C V (if S)Logic and bits
orrs	Rdn, Rmalso shown as: orr	010000 1100 Rm Rdn0x4300 / mask 0xFFC0	Bitwise OR`Rdn = Rdn OR Rm`Flags: N ZLogic and bits
pld	[Rn, #imm12]	111110001001 Rn 1111 imm120xF890F000 / mask 0xFFF0F000	Prefetch of a cache line for reading (hint)`prefetch the cache line at Rn + imm12 (a hint)`Loads and stores
pldw	[Rn, #imm12]	111110001011 Rn 1111 imm120xF8B0F000 / mask 0xFFF0F000	Prefetch of a cache line for writing (hint)`prefetch the cache line at Rn + imm12 (a hint)`Loads and stores
pli	[Rn, #imm12]	111110011001 Rn 1111 imm120xF990F000 / mask 0xFFF0F000	Prefetch of a cache line for instructions (hint)`prefetch the cache line at Rn + imm12 (a hint)`Loads and stores
pop	{registers{, pc}}	1011 110 P register_list0xBC00 / mask 0xFE00	Pop of registers (P: also pc, a return) from the stack`load the registers upward from sp; sp = sp + 4 * count`Stack
push	{registers{, lr}}	1011 010 M register_list0xB400 / mask 0xFE00	Push of registers (M: also lr) onto the stack`sp = sp - 4 * count; store the registers upward from sp`Stack
rbit	Rd, Rm	111110101001 Rm 1111 Rd 1010 Rm0xFA90F0A0 / mask 0xFFF0F0F0	Reversal of the bit order`Rd = reverse_bits(Rm)`Logic and bits
rev	Rd, Rm	1011 1010 00 Rm Rd0xBA00 / mask 0xFFC0	Reversal of the bytes (little/big endian)`Rd = reverse_bytes(Rm)`Logic and bits
rev	Rd, Rm	111110101001 Rm 1111 Rd 1000 Rm0xFA90F080 / mask 0xFFF0F0F0	Reversal of the bytes (little/big endian)`Rd = reverse_bytes(Rm)`Logic and bits
rev16	Rd, Rm	1011 1010 01 Rm Rd0xBA40 / mask 0xFFC0	Reversal of the bytes in each half word`Rd = reverse_bytes_in_each_16_bits(Rm)`Logic and bits
rev16	Rd, Rm	111110101001 Rm 1111 Rd 1001 Rm0xFA90F090 / mask 0xFFF0F0F0	Reversal of the bytes in each half word`Rd = reverse_bytes_in_each_16_bits(Rm)`Logic and bits
revsh	Rd, Rm	1011 1010 11 Rm Rd0xBAC0 / mask 0xFFC0	Reversal of the low two bytes, sign-extended`Rd = sext(reverse_bytes(Rm[15:0]))`Logic and bits
revsh	Rd, Rm	111110101001 Rm 1111 Rd 1011 Rm0xFA90F0B0 / mask 0xFFF0F0F0	Reversal of the low two bytes, sign-extended`Rd = sext(reverse_bytes(Rm[15:0]))`Logic and bits
ror	Rd, Rn, Rm	11111010 0 11 S Rn 1111 Rd 0000 Rm0xFA60F000 / mask 0xFFE0F0F0	Shift right (rotation) by a register (32-bit form)`Rd = rotate_right(Rn, Rm[7:0])`Flags: N Z C (if S)Shift and rotate
rors	Rdn, Rmalso shown as: ror	010000 0111 Rm Rdn0x41C0 / mask 0xFFC0	Rotate right by a register`Rdn = rotate_right(Rdn, Rm[7:0])`Flags: N Z CShift and rotate
rsb	Rd, Rn, #const	11110 i 0 1110 S Rn 0 imm3 Rd imm80xF1C00000 / mask 0xFBE08000	Reverse subtraction: constant as the second operand (8 bit, rotated or repeated)`Rd = const - Rn; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Arithmetic
rsb	Rd, Rn, Rm{, shift #imm}	1110101 1110 S Rn 0 imm3 Rd imm2 type Rm0xEBC00000 / mask 0xFFE08000	Reverse subtraction: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = shift(Rm) - Rn`Flags: N Z C V (if S)Arithmetic
rsbs	Rd, Rn, #0also shown as: neg, rsb	010000 1001 Rn Rd0x4240 / mask 0xFFC0	Reverse subtraction from 0 (negation)`Rd = 0 - Rn`Flags: N Z C VArithmetic
sbc	Rd, Rn, #const	11110 i 0 1011 S Rn 0 imm3 Rd imm80xF1600000 / mask 0xFBE08000	Subtraction with borrow: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn - const - (1 - C); the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Arithmetic
sbc	Rd, Rn, Rm{, shift #imm}	1110101 1011 S Rn 0 imm3 Rd imm2 type Rm0xEB600000 / mask 0xFFE08000	Subtraction with borrow: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn - shift(Rm) - (1 - C)`Flags: N Z C V (if S)Arithmetic
sbcs	Rdn, Rmalso shown as: sbc	010000 0110 Rm Rdn0x4180 / mask 0xFFC0	Subtraction with borrow (C)`Rdn = Rdn - Rm - (1 - C)`Flags: N Z C VArithmetic
sbfx	Rd, Rn, #lsb, #width	11110 0 110100 Rn 0 imm3 Rd imm2 0 widthm10xF3400000 / mask 0xFFF08020	Extraction of a bitfield with sign extension`Rd = sext(Rn[lsb + width - 1 : lsb])`Bitfields
sdiv	Rd, Rn, Rm	111110111001 Rn 1111 Rd 1111 Rm0xFB90F0F0 / mask 0xFFF0F0F0	Signed division (division by 0 gives 0)`Rd = Rn / Rm`Arithmetic
setend	le\|be	10110110 010 E 1 0000xB648 / mask 0xFFEF	Selection of the byte order for data accesses (E = 0: little endian, 1: big endian; deprecated in ARMv8)`data endianness = E`System and privileged
sev		1011 1111 0100 00000xBF40 / mask 0xFFFF	Send of an event to all processors`set the event register of all processors`System and privileged
smlal	RdLo, RdHi, Rn, Rm	111110111100 Rn RdLo RdHi 0000 Rm0xFBC00000 / mask 0xFFF000F0	Signed multiplication to 64 bits with addition`RdHi:RdLo = RdHi:RdLo + sext(Rn) * sext(Rm)`Arithmetic
smull	RdLo, RdHi, Rn, Rm	111110111000 Rn RdLo RdHi 0000 Rm0xFB800000 / mask 0xFFF000F0	Signed multiplication to 64 bits`RdHi:RdLo = sext(Rn) * sext(Rm)`Arithmetic
stm	Rn!, {registers}also shown as: stmia	11000 Rn register_list0xC000 / mask 0xF800	Store of several registers (increasing, Rn is written back)`for each register in the list: [Rn] = reg; Rn = Rn + 4`Loads and stores
stm	Rn{!}, {registers}also shown as: stmia	1110100010 W 0 Rn register_list0xE8800000 / mask 0xFFD00000	Store of several registers (increasing)`for each register in the list: [Rn] = reg; Rn = Rn + 4`Loads and stores
stmdb	Rn{!}, {registers}also shown as: push	1110100100 W 0 Rn register_list0xE9000000 / mask 0xFFD00000	Store of several registers (decreasing; push is stmdb sp!)`for each register in the list, last first: Rn = Rn - 4; [Rn] = reg`Loads and stores
str	Rt, [Rn, Rm]	0101 000 Rm Rn Rt0x5000 / mask 0xFE00	Store of a word (register address)`[Rn + Rm] = Rt`Loads and stores
	Rt, [Rn{, #imm5*4}]	011 00 imm5 Rn Rt0x6000 / mask 0xF800	Store of a word (constant offset)`[Rn + imm5 * 4] = Rt`Loads and stores
	Rt, [sp{, #imm8*4}]	100 10 Rt imm80x9000 / mask 0xF800	Store of a word relative to the stack pointer`[sp + imm8 * 4] = Rt`Loads and stores
	Rt, [Rn, #imm12]	111110001100 Rn Rt imm120xF8C00000 / mask 0xFFF00000	Store of a word (constant, 12 bit, forward only)`[Rn + imm12] = Rt`Loads and stores
	Rt, [Rn, #+/-imm8]{!} / [Rn], #+/-imm8	111110000100 Rn Rt 1 P U W imm80xF8400800 / mask 0xFFF00800	Store of a word (constant, 8 bit, with or without write-back)`[Rn +/- imm8] = Rt`Loads and stores
	Rt, [Rn, Rm{, lsl #imm2}]	111110000100 Rn Rt 000000 imm2 Rm0xF8400000 / mask 0xFFF00FC0	Store of a word (register, optionally shifted left by 0 to 3)`[Rn + (Rm << imm2)] = Rt`Loads and stores
strb	Rt, [Rn, Rm]	0101 010 Rm Rn Rt0x5400 / mask 0xFE00	Store of a byte (register address)`[Rn + Rm] = Rt[7:0]`Loads and stores
	Rt, [Rn{, #imm5}]	011 10 imm5 Rn Rt0x7000 / mask 0xF800	Store of a byte (constant offset)`[Rn + imm5] = Rt[7:0]`Loads and stores
	Rt, [Rn, #imm12]	111110001000 Rn Rt imm120xF8800000 / mask 0xFFF00000	Store of a byte (constant, 12 bit, forward only)`[Rn + imm12] = Rt[7:0]`Loads and stores
	Rt, [Rn, #+/-imm8]{!} / [Rn], #+/-imm8	111110000000 Rn Rt 1 P U W imm80xF8000800 / mask 0xFFF00800	Store of a byte (constant, 8 bit, with or without write-back)`[Rn +/- imm8] = Rt[7:0]`Loads and stores
	Rt, [Rn, Rm{, lsl #imm2}]	111110000000 Rn Rt 000000 imm2 Rm0xF8000000 / mask 0xFFF00FC0	Store of a byte (register, optionally shifted left by 0 to 3)`[Rn + (Rm << imm2)] = Rt[7:0]`Loads and stores
strbt	Rt, [Rn{, #imm8}]	111110000000 Rn Rt 1110 imm80xF8000E00 / mask 0xFFF00F00	Store of a byte with the rights of user mode`[Rn + imm8] = Rt[7:0]`Loads and stores
strd	Rt, Rt2, [Rn, #+/-imm84]{!} / [Rn], #+/-imm84	1110100 P U 1 W 0 Rn Rt Rt2 imm80xE8400000 / mask 0xFE500000	Store of a register pair (two words)`[addr] = Rt; [addr + 4] = Rt2`Loads and stores
strex	Rd, Rt, [Rn{, #imm8*4}]	111010000100 Rn Rt Rd imm80xE8400000 / mask 0xFFF00000	Store-exclusive: Rd = 0 on success`if the exclusive monitor is set then { [Rn + imm8 * 4] = Rt; Rd = 0 } else Rd = 1`Loads and stores
strexb	Rd, Rt, [Rn]	111010001100 Rn Rt 1111 0100 Rd0xE8C00F40 / mask 0xFFF00FF0	Store-exclusive of a byte`if the exclusive monitor is set then { [Rn] = Rt[7:0]; Rd = 0 } else Rd = 1`Loads and stores
strexd	Rd, Rt, Rt2, [Rn]	111010001100 Rn Rt Rt2 0111 Rd0xE8C00070 / mask 0xFFF000F0	Store of a double word (exclusive): only if the monitor is still set`if exclusive then [Rn] = Rt:Rt2; Rd = 0 else Rd = 1`Loads and stores
strexh	Rd, Rt, [Rn]	111010001100 Rn Rt 1111 0101 Rd0xE8C00F50 / mask 0xFFF00FF0	Store-exclusive of a half word`if the exclusive monitor is set then { [Rn] = Rt[15:0]; Rd = 0 } else Rd = 1`Loads and stores
strh	Rt, [Rn, Rm]	0101 001 Rm Rn Rt0x5200 / mask 0xFE00	Store of a half word (register address)`[Rn + Rm] = Rt[15:0]`Loads and stores
	Rt, [Rn{, #imm5*2}]	100 00 imm5 Rn Rt0x8000 / mask 0xF800	Store of a half word (constant offset)`[Rn + imm5 * 2] = Rt[15:0]`Loads and stores
	Rt, [Rn, #imm12]	111110001010 Rn Rt imm120xF8A00000 / mask 0xFFF00000	Store of a half word (constant, 12 bit, forward only)`[Rn + imm12] = Rt[15:0]`Loads and stores
	Rt, [Rn, #+/-imm8]{!} / [Rn], #+/-imm8	111110000010 Rn Rt 1 P U W imm80xF8200800 / mask 0xFFF00800	Store of a half word (constant, 8 bit, with or without write-back)`[Rn +/- imm8] = Rt[15:0]`Loads and stores
	Rt, [Rn, Rm{, lsl #imm2}]	111110000010 Rn Rt 000000 imm2 Rm0xF8200000 / mask 0xFFF00FC0	Store of a half word (register, optionally shifted left by 0 to 3)`[Rn + (Rm << imm2)] = Rt[15:0]`Loads and stores
strht	Rt, [Rn{, #imm8}]	111110000010 Rn Rt 1110 imm80xF8200E00 / mask 0xFFF00F00	Store of a half word with the rights of user mode`[Rn + imm8] = Rt[15:0]`Loads and stores
strt	Rt, [Rn{, #imm8}]	111110000100 Rn Rt 1110 imm80xF8400E00 / mask 0xFFF00F00	Store of a word with the rights of user mode`[Rn + imm8] = Rt`Loads and stores
sub	sp, sp, #imm7*4	1011 0000 1 imm70xB080 / mask 0xFF80	Decrease of the stack pointer`sp = sp - imm7 * 4`Arithmetic
	Rd, Rn, #constalso shown as: cmp	11110 i 0 1101 S Rn 0 imm3 Rd imm80xF1A00000 / mask 0xFBE08000	Subtraction: constant as the second operand (8 bit, rotated or repeated)`Rd = Rn - const; the constant is expanded from i:imm3:imm8`Flags: N Z C V (if S)Arithmetic
	Rd, Rn, Rm{, shift #imm}also shown as: cmp	1110101 1101 S Rn 0 imm3 Rd imm2 type Rm0xEBA00000 / mask 0xFFE08000	Subtraction: register as the second operand, shifted (lsl, lsr, asr, ror, rrx)`Rd = Rn - shift(Rm)`Flags: N Z C V (if S)Arithmetic
subs	Rd, Rn, Rmalso shown as: sub	000 11 0 1 Rm Rn Rd0x1A00 / mask 0xFE00	Subtraction of two registers`Rd = Rn - Rm`Flags: N Z C VArithmetic
	Rd, Rn, #imm3also shown as: sub	000 11 1 1 imm3 Rn Rd0x1E00 / mask 0xFE00	Subtraction of a constant (3 bit)`Rd = Rn - imm3`Flags: N Z C VArithmetic
	Rdn, #imm8also shown as: sub	001 11 Rdn imm80x3800 / mask 0xF800	Subtraction of a constant (8 bit)`Rdn = Rdn - imm8`Flags: N Z C VArithmetic
subw	Rd, Rn, #imm12also shown as: sub	11110 i 101010 Rn 0 imm3 Rd imm80xF2A00000 / mask 0xFBF08000	Subtraction of a constant (12 bit)`Rd = Rn - imm12 (i:imm3:imm8)`Arithmetic
svc	#imm8	1101 1111 imm80xDF00 / mask 0xFF00	Supervisor call to the operating system`raise a supervisor call exception with imm8`System and privileged
sxtab	Rd, Rn, Rm{, ror #rot}also shown as: sxtah, sxtab16, uxtab, uxtah, uxtab16	11111010 0 op Rn 1111 Rd 1 0 rotate Rm0xFA00F080 / mask 0xFF80F0C0	Extension of a byte or half word (sxt: signed, uxt: zero) and addition of Rn; ...16: two half words from two bytes; Rm rotated by 0/8/16/24 first`Rd = Rn + extend(ror(Rm, rot))`Logic and bits
sxtb	Rd, Rm	1011 0010 01 Rm Rd0xB240 / mask 0xFFC0	Sign extension of a byte`Rd = sext(Rm[7:0])`Logic and bits
sxtb	Rd, Rm{, ror #rot}	1111101 00100 1111 1111 Rd 10 rotate Rm0xFA4FF080 / mask 0xFFFFF0C0	Sign extension of a byte (32-bit form, Rm rotated by 0/8/16/24 first)`Rd = sext(rotate(Rm)[7:0])`Logic and bits
sxtb16	Rd, Rm{, ror #rot}also shown as: uxtb16	111110100 01 U 1111 1111 Rd 1 0 rotate Rm0xFA2FF080 / mask 0xFFEFF0C0	Extension of two bytes to two half words (sxt: signed, uxt: zero); Rm rotated by 0/8/16/24 first`Rd = extend(ror(Rm, rot)) per half word`Logic and bits
sxth	Rd, Rm	1011 0010 00 Rm Rd0xB200 / mask 0xFFC0	Sign extension of a half word`Rd = sext(Rm[15:0])`Logic and bits
sxth	Rd, Rm{, ror #rot}	1111101 00000 1111 1111 Rd 10 rotate Rm0xFA0FF080 / mask 0xFFFFF0C0	Sign extension of a half word (32-bit form, Rm rotated by 0/8/16/24 first)`Rd = sext(rotate(Rm)[15:0])`Logic and bits
tbb	[Rn, Rm]	111010001101 Rn 1111 0000 000 0 Rm0xE8D0F000 / mask 0xFFF0FFF0	Jump through a table of byte offsets`pc = pc + 2 * zext([Rn + Rm])`Branches and calls
tbh	[Rn, Rm, lsl #1]	111010001101 Rn 1111 0000 000 1 Rm0xE8D0F010 / mask 0xFFF0FFF0	Jump through a table of half word offsets`pc = pc + 2 * zext([Rn + 2 * Rm])`Branches and calls
tst	Rn, Rm	010000 1000 Rm Rn0x4200 / mask 0xFFC0	Bitwise test (AND), only the flags change`flags = Rn & Rm`Flags: N ZLogic and bits
tt	Rd, Rnalso shown as: tta, ttt, ttat	111010000100 Rn 1111 Rd A T 0000000xE840F000 / mask 0xFFF0F03F	Test of the target of an address (TrustZone: security state and access rights; A: alternate, T: unprivileged)`Rd = security attributes of the address Rn`System and privileged
ubfx	Rd, Rn, #lsb, #width	11110 0 111100 Rn 0 imm3 Rd imm2 0 widthm10xF3C00000 / mask 0xFFF08020	Extraction of a bitfield with zero extension`Rd = zext(Rn[lsb + width - 1 : lsb])`Bitfields
udf	#imm8also shown as: trap	1101 1110 imm80xDE00 / mask 0xFF00	Deliberately undefined instruction (raises an exception)`raise an undefined instruction exception`System and privileged
udf	#imm16	111101111111 imm4 1010 imm120xF7F0A000 / mask 0xFFF0F000	Deliberately undefined instruction (32-bit form)`raise an undefined instruction exception`System and privileged
udiv	Rd, Rn, Rm	111110111011 Rn 1111 Rd 1111 Rm0xFBB0F0F0 / mask 0xFFF0F0F0	Unsigned division (division by 0 gives 0)`Rd = Rn / Rm`Arithmetic
umlal	RdLo, RdHi, Rn, Rm	111110111110 Rn RdLo RdHi 0000 Rm0xFBE00000 / mask 0xFFF000F0	Unsigned multiplication to 64 bits with addition`RdHi:RdLo = RdHi:RdLo + zext(Rn) * zext(Rm)`Arithmetic
umull	RdLo, RdHi, Rn, Rm	111110111010 Rn RdLo RdHi 0000 Rm0xFBA00000 / mask 0xFFF000F0	Unsigned multiplication to 64 bits`RdHi:RdLo = zext(Rn) * zext(Rm)`Arithmetic
uxtb	Rd, Rm	1011 0010 11 Rm Rd0xB2C0 / mask 0xFFC0	Zero extension of a byte`Rd = zext(Rm[7:0])`Logic and bits
uxtb	Rd, Rm{, ror #rot}	1111101 00101 1111 1111 Rd 10 rotate Rm0xFA5FF080 / mask 0xFFFFF0C0	Zero extension of a byte (32-bit form, Rm rotated by 0/8/16/24 first)`Rd = zext(rotate(Rm)[7:0])`Logic and bits
uxth	Rd, Rm	1011 0010 10 Rm Rd0xB280 / mask 0xFFC0	Zero extension of a half word`Rd = zext(Rm[15:0])`Logic and bits
uxth	Rd, Rm{, ror #rot}	1111101 00001 1111 1111 Rd 10 rotate Rm0xFA1FF080 / mask 0xFFFFF0C0	Zero extension of a half word (32-bit form, Rm rotated by 0/8/16/24 first)`Rd = zext(rotate(Rm)[15:0])`Logic and bits
vabs	Vd, Vm	11101110 1 D 11 0000 Vd 101 sz 1 1 M 0 Vm0xEEB00AC0 / mask 0xFFBF0ED0	Floating point: absolute value (sz: 0 = single, 1 = double)`Vd = abs(Vm)`Floating point (VFP)
vadd	Vd, Vn, Vm	11101110 0 D 11 Vn Vd 101 sz N 0 M 0 Vm0xEE300A00 / mask 0xFFB00E50	Floating point: addition (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = Vn + Vm`Floating point (VFP)
vcmp	Vd, Vmalso shown as: vcmpe	11101110 1 D 11 0100 Vd 101 sz E 1 M 0 Vm0xEEB40A40 / mask 0xFFBF0E50	Floating point: comparison of two registers, sets the FPSCR flags (vcmpe: raises an exception on NaN; then vmrs apsr_nzcv, fpscr)`fpscr flags = compare(Vd, Vm)`Flags: N Z C V (FPSCR)Floating point (VFP)
vcmp	Vd, #0.0also shown as: vcmpe	11101110 1 D 11 0101 Vd 101 sz E 1 0 0 00000xEEB50A40 / mask 0xFFBF0E7F	Floating point: comparison with zero, sets the FPSCR flags`fpscr flags = compare(Vd, 0.0)`Flags: N Z C V (FPSCR)Floating point (VFP)
vcvt	Sd, Sm / Dd, Sm	11101110 1 D 11 1000 Vd 101 sz op 1 M 0 Vm0xEEB80A40 / mask 0xFFBF0E50	Floating point: conversion of an integer to floating point (op = 1: signed, 0: unsigned)`Vd = (float) Vm`Floating point (VFP)
	Sd, Sm / Sd, Dmalso shown as: vcvtr	11101110 1 D 11 110 x Vd 101 sz op 1 M 0 Vm0xEEBC0A40 / mask 0xFFBE0E50	Floating point: conversion to an integer (x = 1: signed; op = 1: vcvt, toward zero; op = 0: vcvtr, by the rounding mode)`Vd = (int) Vm`Floating point (VFP)
	Dd, Sm / Sd, Dm	11101110 1 D 11 0111 Vd 101 sz 1 1 M 0 Vm0xEEB70AC0 / mask 0xFFBF0ED0	Floating point: conversion between single and double`Vd = convert(Vm)`Floating point (VFP)
vdiv	Vd, Vn, Vm	11101110 1 D 00 Vn Vd 101 sz N 0 M 0 Vm0xEE800A00 / mask 0xFFB00E50	Floating point: division (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = Vn / Vm`Floating point (VFP)
vfma	Vd, Vn, Vm	11101110 1 D 10 Vn Vd 101 sz N 0 M 0 Vm0xEEA00A00 / mask 0xFFB00E50	Floating point: fused multiplication with addition (no intermediate rounding) (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = Vd + Vn * Vm`Floating point (VFP)
vfms	Vd, Vn, Vm	11101110 1 D 10 Vn Vd 101 sz N 1 M 0 Vm0xEEA00A40 / mask 0xFFB00E50	Floating point: fused multiplication with subtraction (no intermediate rounding) (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = Vd - Vn * Vm`Floating point (VFP)
vfnma	Vd, Vn, Vm	11101110 1 D 01 Vn Vd 101 sz N 1 M 0 Vm0xEE900A40 / mask 0xFFB00E50	Floating point: negated fused multiplication with addition (no intermediate rounding) (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = -Vd - Vn * Vm`Floating point (VFP)
vfnms	Vd, Vn, Vm	11101110 1 D 01 Vn Vd 101 sz N 0 M 0 Vm0xEE900A00 / mask 0xFFB00E50	Floating point: negated fused multiplication with subtraction (no intermediate rounding) (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = -Vd + Vn * Vm`Floating point (VFP)
vldm	Rn{!}, {Sd \| Dd list}also shown as: vldmia, vpop, fldmiax	1110110 0 1 D W 1 Rn Vd 101 sz imm80xEC900A00 / mask 0xFF900E00	Floating point: load of several registers ascending from the address (vldmia; vpop = vldmia sp!; fldmx with an odd count)`registers = [Rn ...]; optionally Rn = Rn + size`Floating point (VFP)
vldmdb	Rn!, {Sd \| Dd list}also shown as: fldmdbx	1110110 1 0 D 1 1 Rn Vd 101 sz imm80xED300A00 / mask 0xFFB00E00	Floating point: load of several registers descending below the address, Rn is decreased (vldmdb)`Rn = Rn - size; registers = [Rn ...]`Floating point (VFP)
vldr	Sd\|Dd, [Rn{, #+/-imm8*4}]	11101101 U D 0 1 Rn Vd 101 sz imm80xED100A00 / mask 0xFF300E00	Floating point: load of a register from memory (sz: 0 = single, 1 = double)`Vd = [Rn +/- imm8 * 4]`Floating point (VFP)
vmla	Vd, Vn, Vm	11101110 0 D 00 Vn Vd 101 sz N 0 M 0 Vm0xEE000A00 / mask 0xFFB00E50	Floating point: multiplication with addition to the destination (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = Vd + Vn * Vm`Floating point (VFP)
vmls	Vd, Vn, Vm	11101110 0 D 00 Vn Vd 101 sz N 1 M 0 Vm0xEE000A40 / mask 0xFFB00E50	Floating point: multiplication with subtraction from the destination (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = Vd - Vn * Vm`Floating point (VFP)
vmov	Vd, Vm	11101110 1 D 11 0000 Vd 101 sz 0 1 M 0 Vm0xEEB00A40 / mask 0xFFBF0ED0	Floating point: copy of a floating point register (sz: 0 = single, 1 = double)`Vd = Vm`Floating point (VFP)
	Sd\|Dd, #imm	11101110 1 D 11 imm4H Vd 101 sz 0 0 0 0 imm4L0xEEB00A00 / mask 0xFFB00EF0	Floating point: load of a constant (8-bit encoded, +-(16..31)/16 * 2^(-3..4))`Vd = constant`Floating point (VFP)
	Sn, Rt / Rt, Sn	11101110 000 op Vn Rt 1010 N 00 1 00000xEE000A10 / mask 0xFFE00F7F	Floating point: copy between an integer register and a single register (bitwise)`Rt = bits(Sn) or Sn = bits(Rt)`Floating point (VFP)
	Sm, Sm1, Rt, Rt2 / Dm, Rt, Rt2	11101100 010 op Rt2 Rt 101 sz 0 0 M 1 Vm0xEC400A10 / mask 0xFFE00ED0	Floating point: copy between two integer registers and two single or one double register`Dm = Rt2:Rt or Rt:Rt2 = Dm`Floating point (VFP)
	Dd[x], Rt / Rt, Dn[x]	11101110 0 0 x L Vn Rt 1011 N 00 1 00000xEE000B10 / mask 0xFFC00F7F	Floating point: copy of a 32-bit word between an integer register and half of a double register`Dd[x] = Rt or Rt = Dn[x]`Floating point (VFP)
vmrs	Rt, FPSID\|FPSCR	111011101111 000 x Rt 1010 0001 00000xEEF00A10 / mask 0xFFFE0FFF	Copy of a floating point system register to an integer register (with Rt = pc: to the APSR flags)`Rt = system register`Floating point (VFP)
vmsr	FPSID\|FPSCR, Rt	111011101110 000 x Rt 1010 0001 00000xEEE00A10 / mask 0xFFFE0FFF	Copy of an integer register to a floating point system register`system register = Rt`Floating point (VFP)
vmul	Vd, Vn, Vm	11101110 0 D 10 Vn Vd 101 sz N 0 M 0 Vm0xEE200A00 / mask 0xFFB00E50	Floating point: multiplication (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = Vn * Vm`Floating point (VFP)
vneg	Vd, Vm	11101110 1 D 11 0001 Vd 101 sz 0 1 M 0 Vm0xEEB10A40 / mask 0xFFBF0ED0	Floating point: sign change (sz: 0 = single, 1 = double)`Vd = -Vm`Floating point (VFP)
vnmla	Vd, Vn, Vm	11101110 0 D 01 Vn Vd 101 sz N 1 M 0 Vm0xEE100A40 / mask 0xFFB00E50	Floating point: negated multiplication with addition (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = -Vd - Vn * Vm`Floating point (VFP)
vnmls	Vd, Vn, Vm	11101110 0 D 01 Vn Vd 101 sz N 0 M 0 Vm0xEE100A00 / mask 0xFFB00E50	Floating point: negated multiplication with subtraction (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = -Vd + Vn * Vm`Floating point (VFP)
vnmul	Vd, Vn, Vm	11101110 0 D 10 Vn Vd 101 sz N 1 M 0 Vm0xEE200A40 / mask 0xFFB00E50	Floating point: negated multiplication (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = -(Vn * Vm)`Floating point (VFP)
vsqrt	Vd, Vm	11101110 1 D 11 0001 Vd 101 sz 1 1 M 0 Vm0xEEB10AC0 / mask 0xFFBF0ED0	Floating point: square root (sz: 0 = single, 1 = double)`Vd = sqrt(Vm)`Floating point (VFP)
vstm	Rn{!}, {Sd \| Dd list}also shown as: vstmia, fstmiax	1110110 0 1 D W 0 Rn Vd 101 sz imm80xEC800A00 / mask 0xFF900E00	Floating point: store of several registers ascending from the address (vstmia; fstmx with an odd count)`[Rn ...] = registers; optionally Rn = Rn + size`Floating point (VFP)
vstmdb	Rn!, {Sd \| Dd list}also shown as: vpush, fstmdbx	1110110 1 0 D 1 0 Rn Vd 101 sz imm80xED200A00 / mask 0xFFB00E00	Floating point: store of several registers descending below the address, Rn is decreased (vstmdb; vpush = vstmdb sp!)`Rn = Rn - size; [Rn ...] = registers`Floating point (VFP)
vstr	Sd\|Dd, [Rn{, #+/-imm8*4}]	11101101 U D 0 0 Rn Vd 101 sz imm80xED000A00 / mask 0xFF300E00	Floating point: store of a register to memory (sz: 0 = single, 1 = double)`[Rn +/- imm8 * 4] = Vd`Floating point (VFP)
vsub	Vd, Vn, Vm	11101110 0 D 11 Vn Vd 101 sz N 1 M 0 Vm0xEE300A40 / mask 0xFFB00E50	Floating point: subtraction (sz = 0: single, Sd/Sn/Sm; sz = 1: double, Dd/Dn/Dm)`Vd = Vn - Vm`Floating point (VFP)
wfe		1011 1111 0010 00000xBF20 / mask 0xFFFF	Wait for event`sleep until an event`System and privileged
wfi		1011 1111 0011 00000xBF30 / mask 0xFFFF	Wait for interrupt`sleep until an interrupt`System and privileged
yield		1011 1111 0001 00000xBF10 / mask 0xFFFF	Hint: spin loop, the processor may switch to another thread`no change (a hint)`System and privileged