ARM64 instructions (AArch64)

Instruction reference: i386 · x64 · ARM32 (Thumb-2) · ARM64 (AArch64)

433 instructions in 635 forms: name, operands, the bit encoding of the 32-bit instruction word (fixed bits and fields) and a short description with the operation in pseudo code. Included are the integer instructions (arithmetic, logic, shifts, bitfields, branches, loads and stores, system instructions), floating point, the vector (SIMD) instructions, the atomic instructions (LSE), memory tagging (MTE), pointer authentication (PAC), CRC, memory copy and set (MOPS) and cryptography (AES, SHA, SM3, SM4). Every instruction that Dismonite decodes is included. Instructions with several names (byte and half word, acquire and release, Q = 1 with the suffix 2) share one row; the other names are listed under the operands after “also shown as”. Not included yet are the scalar forms of the vector instructions (registers B, H, S or D instead of Vn.T), the SVE and SME instructions and the half-precision floating point instructions.

How to read the table

Every ARM64 instruction is exactly 32 bits long. The encoding shows the bits from 31 (left) to 0 (right): 0101 are fixed bits (the opcode), the names are fields. Hover a field to see its range of bits. Rd, Rn, Rm, Ra are registers (number 0 to 31; 31 is sp or xzr/wzr, depending on the instruction), sf chooses 32 bits (0, W registers) or 64 bits (1, X registers), imm… is a constant, cond a condition (4 bits), shift and option choose a kind of shift or extension. Below is the value of the fixed bits and the mask in hex: an instruction word belongs to this form if (word & mask) == value, where the mask leaves the fields out.

Operation: Rd = Rn + Rm and the like is pseudo code; sext and zext extend with sign and with zeros, >>s shifts with sign, [x] is the memory at address x. Aliases: many instructions are usually written in another form (mov, cmp, lsl, cset ...); the disassembler then shows the alias name, the encoding is that of the base form. The names of the fields follow the Arm manual and are not in every case the same.

Every encoding in this table is checked against the decoder of Dismonite: with random values in the fields it gives this instruction (or its alias) again.

Instruction	Operands	Encoding	Description
abs	Vd.T, Vn.T	0 Q 0 01110 size 10000 01011 10 Rn Rd0x0E20B800 / mask 0xBF3FFC00	Absolute value`for every element: Vd[i] = abs(Vn[i])`Vector (SIMD)
adc	Rd, Rn, Rm	sf 0 0 11010000 Rm 000000 Rn Rd0x1A000000 / mask 0x7FE0FC00	Addition with carry (C)`Rd = Rn + Rm + C`Arithmetic
adcs	Rd, Rn, Rm	sf 0 1 11010000 Rm 000000 Rn Rd0x3A000000 / mask 0x7FE0FC00	Addition with carry, sets the flags`Rd = Rn + Rm + C`Flags: N Z C VArithmetic
add	Rd, Rn, #imm12{, lsl #12}also shown as: mov, cmn	sf 0 0 100010 sh imm12 Rn Rd0x11000000 / mask 0x7F800000	Addition of a constant (12 bit, optionally shifted left by 12)`Rd = Rn + (imm12 << (sh * 12)) (Rd and Rn may be SP)`Arithmetic
	Rd, Rn, Rm{, shift #imm6}	sf 0 0 01011 shift 0 Rm imm6 Rn Rd0x0B000000 / mask 0x7F200000	Addition with a shifted register (lsl, lsr, asr)`Rd = Rn + shift(Rm, imm6)`Arithmetic
	Rd, Rn, Rm{, extend #imm3}	sf 0 0 01011 00 1 Rm option imm3 Rn Rd0x0B200000 / mask 0x7FE00000	Addition with an extended register (byte, half word, word)`Rd = Rn + (extend(Rm) << imm3) (Rd and Rn may be SP)`Arithmetic
	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 10000 1 Rn Rd0x0E208400 / mask 0xBF20FC00	Addition of the elements (8, 16, 32 or 64 bit)`for every element: Vd[i] = Vn[i] + Vm[i]`Vector (SIMD)
addg	Xd\|SP, Xn\|SP, #uimm6, #uimm4	1 0 0 100011 0 imm6 00 imm4 Rn Rd0x91800000 / mask 0xFFC0C000	Addition to an address with a change of the tag`Xd = Xn + uimm6 * 16, tag = (tag of Xn + uimm4) modulo 16`Memory tagging (MTE)
addhn	Vd.Tb, Vn.Ta, Vm.Taalso shown as: addhn2	0 Q 0 01110 size 1 Rm 0100 00 Rn Rd0x0E204000 / mask 0xBF20FC00	Addition with narrowing (high half; raddhn with rounding) (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = high half of (Vn[i] + Vm[i])`Vector (SIMD)
addp	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 10111 1 Rn Rd0x0E20BC00 / mask 0xBF20FC00	Addition of adjacent element pairs`for every element: Vd[i] = sum of each pair of (Vn:Vm)`Vector (SIMD)
adds	Rd, Rn, #imm12{, lsl #12}also shown as: cmn	sf 0 1 100010 sh imm12 Rn Rd0x31000000 / mask 0x7F800000	Addition of a constant, sets the flags`Rd = Rn + (imm12 << (sh * 12))`Flags: N Z C VArithmetic
	Rd, Rn, Rm{, shift #imm6}also shown as: cmn	sf 0 1 01011 shift 0 Rm imm6 Rn Rd0x2B000000 / mask 0x7F200000	Addition with a shifted register, sets the flags`Rd = Rn + shift(Rm, imm6)`Flags: N Z C VArithmetic
	Rd, Rn, Rm{, extend #imm3}also shown as: cmn	sf 0 1 01011 00 1 Rm option imm3 Rn Rd0x2B200000 / mask 0x7FE00000	Addition with an extended register, sets the flags`Rd = Rn + (extend(Rm) << imm3)`Flags: N Z C VArithmetic
addv	Vd, Vn.T	0 Q 0 01110 size 11000 11011 10 Rn Rd0x0E31B800 / mask 0xBF3FFC00	Sum of all elements`Vd = sum of all elements of Vn`Vector (SIMD)
adr	Xd, label	0 immlo 10000 immhi Rd0x10000000 / mask 0x9F000000	Address relative to the program counter (+-1 MB)`Xd = pc + sext(immhi:immlo)`Constants and addresses
adrp	Xd, label	1 immlo 10000 immhi Rd0x90000000 / mask 0x9F000000	Address of the 4 KB page relative to the program counter (+-4 GB)`Xd = (pc & ~0xFFF) + (sext(immhi:immlo) << 12)`Constants and addresses
aese	Vd.16B, Vn.16Balso shown as: aesd, aesmc, aesimc	01001110 00 10100 001 op 10 Rn Rd0x4E284800 / mask 0xFFFFCC00	AES encryption: one round (aese, aesmc) or decryption (aesd, aesimc: the counterparts)`aese: Vd = SubBytes(ShiftRows(Vd ^ Vn)); aesmc: Vd = MixColumns(Vn)`Cryptography
and	Rd, Rn, #imm (bit pattern)	sf 0 0 100100 N immr imms Rn Rd0x12000000 / mask 0x7F800000	Bitwise AND with a bit pattern as constant`Rd = Rn & decode_bitmask(N, imms, immr) (Rd may be SP)`Logic and bits
	Rd, Rn, Rm{, shift #imm6}	sf 0 0 01010 shift 0 Rm imm6 Rn Rd0x0A000000 / mask 0x7F200000	Bitwise AND (register, shifted)`Rd = Rn & shift(Rm, imm6)`Logic and bits
	Vd.T, Vn.T, Vm.T	0 Q 0 01110 00 1 Rm 00011 1 Rn Rd0x0E201C00 / mask 0xBFE0FC00	Bitwise AND of two vector registers`Vd = Vn & Vm`Vector (SIMD)
ands	Rd, Rn, #imm (bit pattern)also shown as: tst	sf 1 1 100100 N immr imms Rn Rd0x72000000 / mask 0x7F800000	Bitwise AND with a bit pattern, sets the flags`Rd = Rn & decode_bitmask(N, imms, immr); C = V = 0`Flags: N Z C VLogic and bits
ands	Rd, Rn, Rm{, shift #imm6}also shown as: tst	sf 1 1 01010 shift 0 Rm imm6 Rn Rd0x6A000000 / mask 0x7F200000	Bitwise AND, sets the flags`Rd = Rn & shift(Rm, imm6); C = V = 0`Flags: N Z C VLogic and bits
asrv	Rd, Rn, Rmalso shown as: asr	sf 0 0 11010110 Rm 001010 Rn Rd0x1AC02800 / mask 0x7FE0FC00	Shift right signed by a register`Rd = Rn >>s (Rm mod width)`Shift and rotate
b	label	0 00101 imm260x14000000 / mask 0xFC000000	Jump (relative, +-128 MB)`pc = pc + sext(imm26 << 2)`Branches and calls
b.cond	label	0101010 0 imm19 0 cond0x54000000 / mask 0xFF000010	Conditional jump (relative, +-1 MB)`if cond then pc = pc + sext(imm19 << 2)`Branches and calls
bc	labelalso shown as: bc.eq, bc.ne, bc.hs, bc.lo, bc.mi, bc.pl, bc.vs, bc.vc, bc.hi, bc.ls, bc.ge, bc.lt, bc.gt, bc.le, bc.al, bc.nv	0101010 0 imm19 1 cond0x54000010 / mask 0xFF000010	Conditional branch with the hint that it is consistent (FEAT_HBC)`if cond then pc = pc + imm19 * 4`Jumps, calls and interrupts
bcax	Vd.16B, Vn.16B, Vm.16B, Va.16B	11001110 001 Rm 0 Ra Rn Rd0xCE200000 / mask 0xFFE08000	Bit clear and exclusive OR (SHA-3)`Vd = Vn ^ (Vm & ~Va)`Cryptography
bfm	Rd, Rn, #immr, #immsalso shown as: bfc, bfi, bfxil	sf 0 1 100110 N immr imms Rn Rd0x33000000 / mask 0x7F800000	Bitfield move, the other bits of Rd stay (base form of bfi, bfxil)`Rd = (Rd with the field replaced by the field of Rn)`Bitfields
bic	Rd, Rn, Rm{, shift #imm6}	sf 0 0 01010 shift 1 Rm imm6 Rn Rd0x0A200000 / mask 0x7F200000	Bitwise AND with an inverted operand (bit clear)`Rd = Rn & ~shift(Rm, imm6)`Logic and bits
	Vd.T, Vn.T, Vm.T	0 Q 0 01110 01 1 Rm 00011 1 Rn Rd0x0E601C00 / mask 0xBFE0FC00	Bitwise AND with an inverted operand (bit clear)`Vd = Vn & ~Vm`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 1 0111100000 abc 0 cm 1 01 defgh Rd0x2F001400 / mask 0xBFF89C00	Bitwise clear with a 32-bit constant (one byte, shifted)`Vd = Vd & ~(imm8 << (8 * cm))`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 1 0111100000 abc 10 c 1 01 defgh Rd0x2F009400 / mask 0xBFF8DC00	Bitwise clear with a 16-bit constant (one byte, shifted)`Vd = Vd & ~(imm8 << (8 * c))`Vector (SIMD)
bics	Rd, Rn, Rm{, shift #imm6}	sf 1 1 01010 shift 1 Rm imm6 Rn Rd0x6A200000 / mask 0x7F200000	Bitwise AND with an inverted operand, sets the flags`Rd = Rn & ~shift(Rm, imm6); C = V = 0`Flags: N Z C VLogic and bits
bif	Vd.T, Vn.T, Vm.T	0 Q 1 01110 11 1 Rm 00011 1 Rn Rd0x2EE01C00 / mask 0xBFE0FC00	Bitwise insert if the bit in Vm is clear`Vd = (Vn & ~Vm) \| (Vd & Vm)`Vector (SIMD)
bit	Vd.T, Vn.T, Vm.T	0 Q 1 01110 10 1 Rm 00011 1 Rn Rd0x2EA01C00 / mask 0xBFE0FC00	Bitwise insert if the bit in Vm is set`Vd = (Vn & Vm) \| (Vd & ~Vm)`Vector (SIMD)
bl	label	1 00101 imm260x94000000 / mask 0xFC000000	Call of a function (relative, return address to x30)`x30 = pc + 4; pc = pc + sext(imm26 << 2)`Branches and calls
blr	Xn	1101011 0 0 01 11111 000000 Rn 000000xD63F0000 / mask 0xFFFFFC1F	Call of the function at the address in the register`x30 = pc + 4; pc = Xn`Branches and calls
blraa	Xn, Xm\|SPalso shown as: blrab, blraaz, blrabz	1101011 Z 0 01 11111 0000 1 M Rn Rm0xD63F0800 / mask 0xFEFFF800	Call of an authenticated address (a = key A, b = key B, z = modifier 0)`x30 = pc + 4; pc = aut(Xn, key, Xm)`Pointer authentication (PAC)
br	Xn	1101011 0 0 00 11111 000000 Rn 000000xD61F0000 / mask 0xFFFFFC1F	Jump to the address in the register`pc = Xn`Branches and calls
braa	Xn, Xm\|SPalso shown as: brab, braaz, brabz	1101011 Z 0 00 11111 0000 1 M Rn Rm0xD61F0800 / mask 0xFEFFF800	Jump to an authenticated address (a = key A, b = key B, z = modifier 0)`pc = aut(Xn, key, Xm); jump`Pointer authentication (PAC)
brk	#imm16	11010100 001 imm16 000 000xD4200000 / mask 0xFFE0001F	Breakpoint (debug exception)`raise a breakpoint exception with imm16`System and privileged
bsl	Vd.T, Vn.T, Vm.T	0 Q 1 01110 01 1 Rm 00011 1 Rn Rd0x2E601C00 / mask 0xBFE0FC00	Bitwise select: the destination itself is the mask`Vd = (Vd & Vn) \| (~Vd & Vm)`Vector (SIMD)
cas	Ws, Wt, [Xn\|SP]also shown as: casa, casal, casl, casb, casab, casalb, caslb, cash, casah, casalh, caslh	size 001000 1 A 1 Rs R 11111 Rn Rt0x08A07C00 / mask 0x3FA07C00	Atomic compare and swap: if the memory value equals Ws, Wt is stored; Ws receives the old value (variants: b, h, a, l)`t = [Rn]; if t == Ws then [Rn] = Wt; Ws = t`Atomic memory operations (LSE)
casp	Ws, Ws+1, Wt, Wt+1, [Xn\|SP]also shown as: caspa, caspal, caspl	0 sz 001000 0 A 1 Rs 0 R 11111 Rn Rt 00x08207C00 / mask 0xBFA17C01	Atomic compare and swap of a register pair (variants: a = acquire, l = release)`t = [Rn] (pair); if t == Ws:Ws+1 then [Rn] = Wt:Wt+1; Ws:Ws+1 = t`Atomic memory operations (LSE)
cbnz	Rt, label	sf 011010 1 imm19 Rt0x35000000 / mask 0x7F000000	Jump if the register is not 0`if Rt != 0 then pc = pc + sext(imm19 << 2)`Branches and calls
cbz	Rt, label	sf 011010 0 imm19 Rt0x34000000 / mask 0x7F000000	Jump if the register is 0`if Rt == 0 then pc = pc + sext(imm19 << 2)`Branches and calls
ccmn	Rn, Rm, #nzcv, cond	sf 0 1 11010010 Rm cond 0 0 Rn 0 nzcv0x3A400000 / mask 0x7FE00C10	Conditional compare (addition): flags from Rn + Rm, else from nzcv`if cond then flags = compare(Rn + Rm) else flags = nzcv`Flags: N Z C VCompare and exchange
ccmn	Rn, #imm5, #nzcv, cond	sf 0 1 11010010 imm5 cond 1 0 Rn 0 nzcv0x3A400800 / mask 0x7FE00C10	Conditional compare (addition) with a constant`if cond then flags = compare(Rn + imm5) else flags = nzcv`Flags: N Z C VCompare and exchange
ccmp	Rn, Rm, #nzcv, cond	sf 1 1 11010010 Rm cond 0 0 Rn 0 nzcv0x7A400000 / mask 0x7FE00C10	Conditional compare (subtraction): flags from Rn - Rm, else from nzcv`if cond then flags = compare(Rn - Rm) else flags = nzcv`Flags: N Z C VCompare and exchange
ccmp	Rn, #imm5, #nzcv, cond	sf 1 1 11010010 imm5 cond 1 0 Rn 0 nzcv0x7A400800 / mask 0x7FE00C10	Conditional compare (subtraction) with a constant`if cond then flags = compare(Rn - imm5) else flags = nzcv`Flags: N Z C VCompare and exchange
clrex	{#imm4}	1101010100 0 00 011 0011 CRm 0 10 111110xD503305F / mask 0xFFFFF0FF	Clearing of the exclusive monitor`clear the exclusive monitor`Loads and stores
cls	Rd, Rn	sf 1 0 11010110 00000 000101 Rn Rd0x5AC01400 / mask 0x7FFFFC00	Count of the leading bits equal to the sign bit`Rd = count_leading_sign_bits(Rn)`Logic and bits
cls	Vd.T, Vn.T	0 Q 0 01110 size 10000 00100 10 Rn Rd0x0E204800 / mask 0xBF3FFC00	Count of the leading bits equal to the sign bit`for every element: Vd[i] = count_leading_sign_bits(Vn[i])`Vector (SIMD)
clz	Rd, Rn	sf 1 0 11010110 00000 000100 Rn Rd0x5AC01000 / mask 0x7FFFFC00	Count of the leading zero bits`Rd = count_leading_zeros(Rn)`Logic and bits
clz	Vd.T, Vn.T	0 Q 1 01110 size 10000 00100 10 Rn Rd0x2E204800 / mask 0xBF3FFC00	Count of the leading zeros`for every element: Vd[i] = count_leading_zeros(Vn[i])`Vector (SIMD)
cmeq	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 10001 1 Rn Rd0x2E208C00 / mask 0xBF20FC00	Comparison for equal, the result is a mask`for every element: Vd[i] = (Vn[i] == Vm[i]) ? all 1 bits : 0`Vector (SIMD)
cmeq	Vd.T, Vn.T, #0	0 Q 0 01110 size 10000 01001 10 Rn Rd0x0E209800 / mask 0xBF3FFC00	Comparison for equal to zero, the result is a mask`for every element: Vd[i] = (Vn[i] == 0) ? all 1 bits : 0`Vector (SIMD)
cmge	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 00111 1 Rn Rd0x0E203C00 / mask 0xBF20FC00	Comparison for greater or equal (signed), the result is a mask`for every element: Vd[i] = (Vn[i] >= Vm[i]) ? all 1 bits : 0`Vector (SIMD)
cmge	Vd.T, Vn.T, #0	0 Q 1 01110 size 10000 01000 10 Rn Rd0x2E208800 / mask 0xBF3FFC00	Comparison for greater than or equal to zero, the result is a mask`for every element: Vd[i] = (Vn[i] >= 0) ? all 1 bits : 0`Vector (SIMD)
cmgt	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 00110 1 Rn Rd0x0E203400 / mask 0xBF20FC00	Comparison for greater (signed), the result is a mask`for every element: Vd[i] = (Vn[i] > Vm[i]) ? all 1 bits : 0`Vector (SIMD)
cmgt	Vd.T, Vn.T, #0	0 Q 0 01110 size 10000 01000 10 Rn Rd0x0E208800 / mask 0xBF3FFC00	Comparison for greater than zero, the result is a mask`for every element: Vd[i] = (Vn[i] > 0) ? all 1 bits : 0`Vector (SIMD)
cmhi	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 00110 1 Rn Rd0x2E203400 / mask 0xBF20FC00	Comparison for higher (unsigned), the result is a mask`for every element: Vd[i] = (Vn[i] > Vm[i]) ? all 1 bits : 0`Vector (SIMD)
cmhs	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 00111 1 Rn Rd0x2E203C00 / mask 0xBF20FC00	Comparison for higher or same (unsigned), the result is a mask`for every element: Vd[i] = (Vn[i] >= Vm[i]) ? all 1 bits : 0`Vector (SIMD)
cmle	Vd.T, Vn.T, #0	0 Q 1 01110 size 10000 01001 10 Rn Rd0x2E209800 / mask 0xBF3FFC00	Comparison for less than or equal to zero, the result is a mask`for every element: Vd[i] = (Vn[i] <= 0) ? all 1 bits : 0`Vector (SIMD)
cmlt	Vd.T, Vn.T, #0	0 Q 0 01110 size 10000 01010 10 Rn Rd0x0E20A800 / mask 0xBF3FFC00	Comparison for less than zero, the result is a mask`for every element: Vd[i] = (Vn[i] < 0) ? all 1 bits : 0`Vector (SIMD)
cmtst	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 10001 1 Rn Rd0x0E208C00 / mask 0xBF20FC00	Test for common set bits, the result is a mask`for every element: Vd[i] = ((Vn[i] & Vm[i]) != 0) ? all 1 bits : 0`Vector (SIMD)
cnt	Vd.T, Vn.T	0 Q 0 01110 00 10000 00101 10 Rn Rd0x0E205800 / mask 0xBFFFFC00	Count of the set bits in every byte`for every element: Vd[i] = popcount(Vn[i])`Vector (SIMD)
cpye	[Xd]!, [Xs]!, Xn!also shown as: cpyewn, cpyern, cpyen, cpyewt, cpyewtwn, cpyewtrn, cpyewtn, cpyert, cpyertwn, cpyertrn, cpyertn, cpyet, cpyetwn, cpyetrn, cpyetn	00 011 1 01 10 0 Rs op2 01 Rn Rd0x1D800400 / mask 0xFFE00C00	Copy of a memory block, epilogue (the three instructions p, m, e are executed in sequence)`copy Xn bytes from [Xs] to [Xd]; Xd, Xs, Xn are updated`Memory copy and set
cpyfe	[Xd]!, [Xs]!, Xn!also shown as: cpyfewn, cpyfern, cpyfen, cpyfewt, cpyfewtwn, cpyfewtrn, cpyfewtn, cpyfert, cpyfertwn, cpyfertrn, cpyfertn, cpyfet, cpyfetwn, cpyfetrn, cpyfetn	00 011 0 01 10 0 Rs op2 01 Rn Rd0x19800400 / mask 0xFFE00C00	Copy of a memory block, epilogue, forward only (the three instructions p, m, e are executed in sequence)`copy Xn bytes from [Xs] to [Xd]; Xd, Xs, Xn are updated`Memory copy and set
cpyfm	[Xd]!, [Xs]!, Xn!also shown as: cpyfmwn, cpyfmrn, cpyfmn, cpyfmwt, cpyfmwtwn, cpyfmwtrn, cpyfmwtn, cpyfmrt, cpyfmrtwn, cpyfmrtrn, cpyfmrtn, cpyfmt, cpyfmtwn, cpyfmtrn, cpyfmtn	00 011 0 01 01 0 Rs op2 01 Rn Rd0x19400400 / mask 0xFFE00C00	Copy of a memory block, main part, forward only (the three instructions p, m, e are executed in sequence)`copy Xn bytes from [Xs] to [Xd]; Xd, Xs, Xn are updated`Memory copy and set
cpyfp	[Xd]!, [Xs]!, Xn!also shown as: cpyfpwn, cpyfprn, cpyfpn, cpyfpwt, cpyfpwtwn, cpyfpwtrn, cpyfpwtn, cpyfprt, cpyfprtwn, cpyfprtrn, cpyfprtn, cpyfpt, cpyfptwn, cpyfptrn, cpyfptn	00 011 0 01 00 0 Rs op2 01 Rn Rd0x19000400 / mask 0xFFE00C00	Copy of a memory block, prologue, forward only (the three instructions p, m, e are executed in sequence)`copy Xn bytes from [Xs] to [Xd]; Xd, Xs, Xn are updated`Memory copy and set
cpym	[Xd]!, [Xs]!, Xn!also shown as: cpymwn, cpymrn, cpymn, cpymwt, cpymwtwn, cpymwtrn, cpymwtn, cpymrt, cpymrtwn, cpymrtrn, cpymrtn, cpymt, cpymtwn, cpymtrn, cpymtn	00 011 1 01 01 0 Rs op2 01 Rn Rd0x1D400400 / mask 0xFFE00C00	Copy of a memory block, main part (the three instructions p, m, e are executed in sequence)`copy Xn bytes from [Xs] to [Xd]; Xd, Xs, Xn are updated`Memory copy and set
cpyp	[Xd]!, [Xs]!, Xn!also shown as: cpypwn, cpyprn, cpypn, cpypwt, cpypwtwn, cpypwtrn, cpypwtn, cpyprt, cpyprtwn, cpyprtrn, cpyprtn, cpypt, cpyptwn, cpyptrn, cpyptn	00 011 1 01 00 0 Rs op2 01 Rn Rd0x1D000400 / mask 0xFFE00C00	Copy of a memory block, prologue (the three instructions p, m, e are executed in sequence)`copy Xn bytes from [Xs] to [Xd]; Xd, Xs, Xn are updated`Memory copy and set
crc32b	Wd, Wn, Wm	0 0 0 11010110 Rm 010 0 00 Rn Rd0x1AC04000 / mask 0xFFE0FC00	CRC-32 checksum (polynomial 0x04C11DB7) of a byte`Wd = crc32(Wn, Wm)`CRC checksums
crc32cb	Wd, Wn, Wm	0 0 0 11010110 Rm 010 1 00 Rn Rd0x1AC05000 / mask 0xFFE0FC00	CRC-32C checksum (Castagnoli, polynomial 0x1EDC6F41) of a byte`Wd = crc32c(Wn, Wm)`CRC checksums
crc32ch	Wd, Wn, Wm	0 0 0 11010110 Rm 010 1 01 Rn Rd0x1AC05400 / mask 0xFFE0FC00	CRC-32C checksum (Castagnoli, polynomial 0x1EDC6F41) of a half word`Wd = crc32c(Wn, Wm)`CRC checksums
crc32cw	Wd, Wn, Wm	0 0 0 11010110 Rm 010 1 10 Rn Rd0x1AC05800 / mask 0xFFE0FC00	CRC-32C checksum (Castagnoli, polynomial 0x1EDC6F41) of a word`Wd = crc32c(Wn, Wm)`CRC checksums
crc32cx	Wd, Wn, Xm	1 0 0 11010110 Rm 010 1 11 Rn Rd0x9AC05C00 / mask 0xFFE0FC00	CRC-32C checksum (Castagnoli, polynomial 0x1EDC6F41) of a double word`Wd = crc32c(Wn, Xm)`CRC checksums
crc32h	Wd, Wn, Wm	0 0 0 11010110 Rm 010 0 01 Rn Rd0x1AC04400 / mask 0xFFE0FC00	CRC-32 checksum (polynomial 0x04C11DB7) of a half word`Wd = crc32(Wn, Wm)`CRC checksums
crc32w	Wd, Wn, Wm	0 0 0 11010110 Rm 010 0 10 Rn Rd0x1AC04800 / mask 0xFFE0FC00	CRC-32 checksum (polynomial 0x04C11DB7) of a word`Wd = crc32(Wn, Wm)`CRC checksums
crc32x	Wd, Wn, Xm	1 0 0 11010110 Rm 010 0 11 Rn Rd0x9AC04C00 / mask 0xFFE0FC00	CRC-32 checksum (polynomial 0x04C11DB7) of a double word`Wd = crc32(Wn, Xm)`CRC checksums
csel	Rd, Rn, Rm, cond	sf 0 0 11010100 Rm cond 0 0 Rn Rd0x1A800000 / mask 0x7FE00C00	Conditional select (Rn if the condition holds, else Rm)`Rd = cond ? Rn : Rm`Conditional select
csinc	Rd, Rn, Rm, condalso shown as: cinc, cset	sf 0 0 11010100 Rm cond 0 1 Rn Rd0x1A800400 / mask 0x7FE00C00	Conditional select, else Rm + 1 (cset, cinc)`Rd = cond ? Rn : Rm + 1`Conditional select
csinv	Rd, Rn, Rm, condalso shown as: cinv, csetm	sf 1 0 11010100 Rm cond 0 0 Rn Rd0x5A800000 / mask 0x7FE00C00	Conditional select, else the inverted Rm`Rd = cond ? Rn : ~Rm`Conditional select
csneg	Rd, Rn, Rm, condalso shown as: cneg	sf 1 0 11010100 Rm cond 0 1 Rn Rd0x5A800400 / mask 0x7FE00C00	Conditional select, else the negated Rm`Rd = cond ? Rn : -Rm`Conditional select
dcps1	{#imm16}also shown as: dcps2, dcps3	11010100 101 imm16 000 opc0xD4A00000 / mask 0xFFE0001C	Switch to the debug state at exception level 1, 2 or 3 (only in debug state)`enter debug state at EL1, EL2 or EL3`System and privileged
dmb	option	1101010100 0 00 011 0011 CRm 1 01 111110xD50330BF / mask 0xFFFFF0FF	Memory barrier for the order of the accesses`earlier memory accesses are observed before later ones`System and privileged
dsb	optionalso shown as: ssbb, pssbb	1101010100 0 00 011 0011 CRm 1 00 111110xD503309F / mask 0xFFFFF0FF	Memory barrier: waits until all accesses are complete`wait until all earlier memory accesses are complete`System and privileged
dup	Vd.T, Rnalso shown as: mov	0 Q 0 01110000 imm5 0 0001 1 Rn Rd0x0E000C00 / mask 0xBFE0FC00	Copy of an integer register into all elements`for every element: Vd[i] = Rn`Vector (SIMD)
dup	Vd.T, Vn.Ts[index]also shown as: mov	0 Q 0 01110000 imm5 0 0000 1 Rn Rd0x0E000400 / mask 0xBFE0FC00	Copy of one element into all elements`for every element: Vd[i] = Vn[index]`Vector (SIMD)
eon	Rd, Rn, Rm{, shift #imm6}	sf 1 0 01010 shift 1 Rm imm6 Rn Rd0x4A200000 / mask 0x7F200000	Bitwise exclusive OR with an inverted operand`Rd = Rn ^ ~shift(Rm, imm6)`Logic and bits
eor	Rd, Rn, #imm (bit pattern)	sf 1 0 100100 N immr imms Rn Rd0x52000000 / mask 0x7F800000	Bitwise exclusive OR with a bit pattern as constant`Rd = Rn ^ decode_bitmask(N, imms, immr) (Rd may be SP)`Logic and bits
	Rd, Rn, Rm{, shift #imm6}	sf 1 0 01010 shift 0 Rm imm6 Rn Rd0x4A000000 / mask 0x7F200000	Bitwise exclusive OR (register, shifted)`Rd = Rn ^ shift(Rm, imm6)`Logic and bits
	Vd.T, Vn.T, Vm.T	0 Q 1 01110 00 1 Rm 00011 1 Rn Rd0x2E201C00 / mask 0xBFE0FC00	Bitwise exclusive OR`Vd = Vn ^ Vm`Vector (SIMD)
eor3	Vd.16B, Vn.16B, Vm.16B, Va.16B	11001110 000 Rm 0 Ra Rn Rd0xCE000000 / mask 0xFFE08000	Exclusive OR of three vectors (SHA-3)`Vd = Vn ^ Vm ^ Va`Cryptography
eret		1101011 0 100 11111 000000 11111 000000xD69F03E0 / mask 0xFFFFFFFF	Return from an exception (privileged)`pc = ELR; PSTATE = SPSR`Branches and calls
ext	Vd.T, Vn.T, Vm.T, #index	0 Q 101110 00 0 Rm 0 imm4 0 Rn Rd0x2E000000 / mask 0xBFE08400	Extraction of a byte range from two concatenated vectors`Vd = bytes index ... index + 15 of (Vm:Vn)`Vector (SIMD)
extr	Rd, Rn, Rm, #lsbalso shown as: ror	sf 0 0 100111 N 0 Rm imms Rn Rd0x13800000 / mask 0x7FA00000	Extract from the register pair Rn:Rm from bit lsb (ror if Rn = Rm)`Rd = (Rn:Rm >> imms) low half`Shift and rotate
fabd	Vd.T, Vn.T, Vm.T	0 Q 1 01110 1 sz 1 Rm 11010 1 Rn Rd0x2EA0D400 / mask 0xBFA0FC00	Absolute difference of floating point elements`for every element: Vd[i] = abs(Vn[i] - Vm[i])`Vector (SIMD)
fabs	Fd, Fn	0 0 0 11110 ftype 1 000001 10000 Rn Rd0x1E20C000 / mask 0xFF3FFC00	Absolute value`Fd = abs(Fn)`Floating point (scalar)
fabs	Vd.T, Vn.T	0 Q 0 01110 1 sz 10000 01111 10 Rn Rd0x0EA0F800 / mask 0xBFBFFC00	Absolute value of floating point elements`for every element: Vd[i] = abs(Vn[i])`Vector (SIMD)
facge	Vd.T, Vn.T, Vm.T	0 Q 1 01110 0 sz 1 Rm 11101 1 Rn Rd0x2E20EC00 / mask 0xBFA0FC00	Comparison of the absolute values for greater or equal, the result is a mask`for every element: Vd[i] = (abs(Vn[i]) >= abs(Vm[i])) ? all 1 bits : 0`Vector (SIMD)
facgt	Vd.T, Vn.T, Vm.T	0 Q 1 01110 1 sz 1 Rm 11101 1 Rn Rd0x2EA0EC00 / mask 0xBFA0FC00	Comparison of the absolute values for greater, the result is a mask`for every element: Vd[i] = (abs(Vn[i]) > abs(Vm[i])) ? all 1 bits : 0`Vector (SIMD)
fadd	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 0010 10 Rn Rd0x1E202800 / mask 0xFF20FC00	Addition`Fd = Fn + Fm`Floating point (scalar)
fadd	Vd.T, Vn.T, Vm.T	0 Q 0 01110 0 sz 1 Rm 11010 1 Rn Rd0x0E20D400 / mask 0xBFA0FC00	Addition of floating point elements (sz: 0 = single, 1 = double)`for every element: Vd[i] = Vn[i] + Vm[i]`Vector (SIMD)
faddp	Vd.T, Vn.T, Vm.T	0 Q 1 01110 0 sz 1 Rm 11010 1 Rn Rd0x2E20D400 / mask 0xBFA0FC00	Addition of adjacent floating point pairs`for every element: Vd[i] = sum of each pair of (Vn:Vm)`Vector (SIMD)
fcadd	Vd.T, Vn.T, Vm.T, #rot	0 Q 1 01110 size 0 Rm 1 11 rot 0 1 Rn Rd0x2E00E400 / mask 0xBF20EC00	Addition of complex numbers with a rotation by 90 or 270 degrees`Vd = Vn + rotate(Vm, rot)`Vector (SIMD)
fccmp	Fn, Fm, #nzcv, cond	0 0 0 11110 ftype 1 Rm cond 01 Rn 0 nzcv0x1E200400 / mask 0xFF200C10	Conditional compare: flags from Fn, Fm, else from nzcv`if cond then flags = compare(Fn, Fm) else flags = nzcv`Flags: N Z C VFloating point (scalar)
fccmpe	Fn, Fm, #nzcv, cond	0 0 0 11110 ftype 1 Rm cond 01 Rn 1 nzcv0x1E200410 / mask 0xFF200C10	Conditional floating point comparison (with an exception on NaN)`if cond then flags = compare(Fn, Fm) else flags = nzcv`Flags: N Z C VFloating point (scalar)
fcmeq	Vd.T, Vn.T, Vm.T	0 Q 0 01110 0 sz 1 Rm 11100 1 Rn Rd0x0E20E400 / mask 0xBFA0FC00	Floating point comparison for equal, the result is a mask`for every element: Vd[i] = (Vn[i] == Vm[i]) ? all 1 bits : 0`Vector (SIMD)
fcmeq	Vd.T, Vn.T, #0	0 Q 0 01110 1 sz 10000 01101 10 Rn Rd0x0EA0D800 / mask 0xBFBFFC00	Floating point comparison with zero for equal, the result is a mask`for every element: Vd[i] = (Vn[i] == 0) ? all 1 bits : 0`Vector (SIMD)
fcmge	Vd.T, Vn.T, Vm.T	0 Q 1 01110 0 sz 1 Rm 11100 1 Rn Rd0x2E20E400 / mask 0xBFA0FC00	Floating point comparison for greater or equal, the result is a mask`for every element: Vd[i] = (Vn[i] >= Vm[i]) ? all 1 bits : 0`Vector (SIMD)
fcmge	Vd.T, Vn.T, #0	0 Q 1 01110 1 sz 10000 01100 10 Rn Rd0x2EA0C800 / mask 0xBFBFFC00	Floating point comparison with zero for greater or equal, the result is a mask`for every element: Vd[i] = (Vn[i] >= 0) ? all 1 bits : 0`Vector (SIMD)
fcmgt	Vd.T, Vn.T, Vm.T	0 Q 1 01110 1 sz 1 Rm 11100 1 Rn Rd0x2EA0E400 / mask 0xBFA0FC00	Floating point comparison for greater, the result is a mask`for every element: Vd[i] = (Vn[i] > Vm[i]) ? all 1 bits : 0`Vector (SIMD)
fcmgt	Vd.T, Vn.T, #0	0 Q 0 01110 1 sz 10000 01100 10 Rn Rd0x0EA0C800 / mask 0xBFBFFC00	Floating point comparison with zero for greater, the result is a mask`for every element: Vd[i] = (Vn[i] > 0) ? all 1 bits : 0`Vector (SIMD)
fcmla	Vd.T, Vn.T, Vm.T, #rot	0 Q 1 01110 size 0 Rm 1 1 0 rot 1 Rn Rd0x2E00C400 / mask 0xBF20E400	Multiplication of complex numbers (one partial step, rotation 0, 90, 180 or 270 degrees), added to the destination`Vd = Vd + partial_product(Vn, Vm, rot)`Vector (SIMD)
fcmle	Vd.T, Vn.T, #0	0 Q 1 01110 1 sz 10000 01101 10 Rn Rd0x2EA0D800 / mask 0xBFBFFC00	Floating point comparison with zero for less or equal, the result is a mask`for every element: Vd[i] = (Vn[i] <= 0) ? all 1 bits : 0`Vector (SIMD)
fcmlt	Vd.T, Vn.T, #0	0 Q 0 01110 1 sz 10000 01110 10 Rn Rd0x0EA0E800 / mask 0xBFBFFC00	Floating point comparison with zero for less, the result is a mask`for every element: Vd[i] = (Vn[i] < 0) ? all 1 bits : 0`Vector (SIMD)
fcmp	Fn, Fm	0 0 0 11110 ftype 1 Rm 001000 Rn 00 0000x1E202000 / mask 0xFF20FC1F	Comparison of two floating point values, sets the flags`flags = compare(Fn, Fm) (unordered: N Z C V = 0 0 1 1)`Flags: N Z C VFloating point (scalar)
fcmp	Fn, #0.0	0 0 0 11110 ftype 1 00000 001000 Rn 01 0000x1E202008 / mask 0xFF3FFC1F	Comparison with 0.0, sets the flags`flags = compare(Fn, 0.0)`Flags: N Z C VFloating point (scalar)
fcmpe	Fn, Fm	0 0 0 11110 ftype 1 Rm 001000 Rn 10 0000x1E202010 / mask 0xFF20FC1F	Comparison raising an exception on NaN (signalling), sets the flags`flags = compare(Fn, Fm)`Flags: N Z C VFloating point (scalar)
fcsel	Fd, Fn, Fm, cond	0 0 0 11110 ftype 1 Rm cond 11 Rn Rd0x1E200C00 / mask 0xFF200C00	Conditional select (Fn if the condition holds, else Fm)`Fd = cond ? Fn : Fm`Floating point (scalar)
fcvt	Fd, Fn	0 0 0 11110 ftype 1 0001 opc 10000 Rn Rd0x1E224000 / mask 0xFF3E7C00	Conversion between precisions (half, single, double)`Fd = convert(Fn) to the precision of Fd`Floating point (scalar)
fcvtas	Rd, Fn	sf 0 0 11110 ftype 1 00 100 000000 Rn Rd0x1E240000 / mask 0x7F3FFC00	Conversion to a signed integer (to nearest, ties away from zero)`Rd = (int) round_half_away(Fn)`Floating point (scalar)
fcvtas	Vd.T, Vn.T	0 Q 0 01110 0 sz 10000 11100 10 Rn Rd0x0E21C800 / mask 0xBFBFFC00	Conversion to a signed integer (to nearest, ties away from zero)`for every element: Vd[i] = (int) round_half_away(Vn[i])`Vector (SIMD)
fcvtau	Rd, Fn	sf 0 0 11110 ftype 1 00 101 000000 Rn Rd0x1E250000 / mask 0x7F3FFC00	Conversion to an unsigned integer (to nearest, ties away from zero)`Rd = (uint) round_half_away(Fn)`Floating point (scalar)
fcvtau	Vd.T, Vn.T	0 Q 1 01110 0 sz 10000 11100 10 Rn Rd0x2E21C800 / mask 0xBFBFFC00	Conversion to an unsigned integer (to nearest, ties away from zero)`for every element: Vd[i] = (uint) round_half_away(Vn[i])`Vector (SIMD)
fcvtl	Vd.Ta, Vn.Tbalso shown as: fcvtl2	0 Q 0 01110 0 sz 10000 10111 10 Rn Rd0x0E217800 / mask 0xBFBFFC00	Conversion to twice the precision`for every element: Vd[i] = convert(Vn[i]) wider`Vector (SIMD)
fcvtms	Rd, Fn	sf 0 0 11110 ftype 1 10 000 000000 Rn Rd0x1E300000 / mask 0x7F3FFC00	Conversion to a signed integer (toward minus infinity)`Rd = (int) floor(Fn)`Floating point (scalar)
fcvtms	Vd.T, Vn.T	0 Q 0 01110 0 sz 10000 11011 10 Rn Rd0x0E21B800 / mask 0xBFBFFC00	Conversion to a signed integer (toward minus infinity)`for every element: Vd[i] = (int) floor(Vn[i])`Vector (SIMD)
fcvtmu	Rd, Fn	sf 0 0 11110 ftype 1 10 001 000000 Rn Rd0x1E310000 / mask 0x7F3FFC00	Conversion to an unsigned integer (toward minus infinity)`Rd = (uint) floor(Fn)`Floating point (scalar)
fcvtmu	Vd.T, Vn.T	0 Q 1 01110 0 sz 10000 11011 10 Rn Rd0x2E21B800 / mask 0xBFBFFC00	Conversion to an unsigned integer (toward minus infinity)`for every element: Vd[i] = (uint) floor(Vn[i])`Vector (SIMD)
fcvtn	Vd.Tb, Vn.Taalso shown as: fcvtn2	0 Q 0 01110 0 sz 10000 10110 10 Rn Rd0x0E216800 / mask 0xBFBFFC00	Conversion to half the precision`for every element: Vd[i] = convert(Vn[i]) narrower`Vector (SIMD)
fcvtns	Rd, Fn	sf 0 0 11110 ftype 1 00 000 000000 Rn Rd0x1E200000 / mask 0x7F3FFC00	Conversion to a signed integer (to nearest, even on a tie)`Rd = (int) round_to_nearest_even(Fn)`Floating point (scalar)
fcvtns	Vd.T, Vn.T	0 Q 0 01110 0 sz 10000 11010 10 Rn Rd0x0E21A800 / mask 0xBFBFFC00	Conversion to a signed integer (to nearest, even on a tie)`for every element: Vd[i] = (int) round_to_nearest_even(Vn[i])`Vector (SIMD)
fcvtnu	Rd, Fn	sf 0 0 11110 ftype 1 00 001 000000 Rn Rd0x1E210000 / mask 0x7F3FFC00	Conversion to an unsigned integer (to nearest, even on a tie)`Rd = (uint) round_to_nearest_even(Fn)`Floating point (scalar)
fcvtnu	Vd.T, Vn.T	0 Q 1 01110 0 sz 10000 11010 10 Rn Rd0x2E21A800 / mask 0xBFBFFC00	Conversion to an unsigned integer (to nearest, even on a tie)`for every element: Vd[i] = (uint) round_to_nearest_even(Vn[i])`Vector (SIMD)
fcvtps	Rd, Fn	sf 0 0 11110 ftype 1 01 000 000000 Rn Rd0x1E280000 / mask 0x7F3FFC00	Conversion to a signed integer (toward plus infinity)`Rd = (int) ceil(Fn)`Floating point (scalar)
fcvtps	Vd.T, Vn.T	0 Q 0 01110 1 sz 10000 11010 10 Rn Rd0x0EA1A800 / mask 0xBFBFFC00	Conversion to a signed integer (toward plus infinity)`for every element: Vd[i] = (int) ceil(Vn[i])`Vector (SIMD)
fcvtpu	Rd, Fn	sf 0 0 11110 ftype 1 01 001 000000 Rn Rd0x1E290000 / mask 0x7F3FFC00	Conversion to an unsigned integer (toward plus infinity)`Rd = (uint) ceil(Fn)`Floating point (scalar)
fcvtpu	Vd.T, Vn.T	0 Q 1 01110 1 sz 10000 11010 10 Rn Rd0x2EA1A800 / mask 0xBFBFFC00	Conversion to an unsigned integer (toward plus infinity)`for every element: Vd[i] = (uint) ceil(Vn[i])`Vector (SIMD)
fcvtxn	Vd.Tb, Vn.Taalso shown as: fcvtxn2	0 Q 1 01110 0 sz 10000 10110 10 Rn Rd0x2E216800 / mask 0xBFBFFC00	Conversion to half the precision (round to odd)`for every element: Vd[i] = convert_round_to_odd(Vn[i])`Vector (SIMD)
fcvtzs	Rd, Fn	sf 0 0 11110 ftype 1 11 000 000000 Rn Rd0x1E380000 / mask 0x7F3FFC00	Conversion to a signed integer (truncated, toward zero)`Rd = (int) trunc(Fn)`Floating point (scalar)
fcvtzs	Vd.T, Vn.T	0 Q 0 01110 1 sz 10000 11011 10 Rn Rd0x0EA1B800 / mask 0xBFBFFC00	Conversion to a signed integer (toward zero)`for every element: Vd[i] = (int) trunc(Vn[i])`Vector (SIMD)
fcvtzu	Rd, Fn	sf 0 0 11110 ftype 1 11 001 000000 Rn Rd0x1E390000 / mask 0x7F3FFC00	Conversion to an unsigned integer (truncated, toward zero)`Rd = (uint) trunc(Fn)`Floating point (scalar)
fcvtzu	Vd.T, Vn.T	0 Q 1 01110 1 sz 10000 11011 10 Rn Rd0x2EA1B800 / mask 0xBFBFFC00	Conversion to an unsigned integer (toward zero)`for every element: Vd[i] = (uint) trunc(Vn[i])`Vector (SIMD)
fdiv	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 0001 10 Rn Rd0x1E201800 / mask 0xFF20FC00	Division`Fd = Fn / Fm`Floating point (scalar)
fdiv	Vd.T, Vn.T, Vm.T	0 Q 1 01110 0 sz 1 Rm 11111 1 Rn Rd0x2E20FC00 / mask 0xBFA0FC00	Division of floating point elements`for every element: Vd[i] = Vn[i] / Vm[i]`Vector (SIMD)
fjcvtzs	Wd, Dn	0 0 0 11110 01 1 11 110 000000 Rn Rd0x1E7E0000 / mask 0xFFFFFC00	Conversion to an integer by JavaScript rules (result modulo 2^32)`Wd = javascript_to_int32(Dn)`Flags: N Z C VPointer authentication (PAC)
fmadd	Fd, Fn, Fm, Fa	0 0 0 11111 ftype 0 Rm 0 Ra Rn Rd0x1F000000 / mask 0xFF208000	Multiply and add (fused, Fa + Fn * Fm)`Fd = Fa + Fn * Fm`Floating point (scalar)
fmax	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 0100 10 Rn Rd0x1E204800 / mask 0xFF20FC00	Maximum (NaN propagates)`Fd = max(Fn, Fm)`Floating point (scalar)
fmax	Vd.T, Vn.T, Vm.T	0 Q 0 01110 0 sz 1 Rm 11110 1 Rn Rd0x0E20F400 / mask 0xBFA0FC00	Maximum of floating point elements`for every element: Vd[i] = max(Vn[i], Vm[i])`Vector (SIMD)
fmaxnm	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 0110 10 Rn Rd0x1E206800 / mask 0xFF20FC00	Maximum (a number wins against NaN)`Fd = maxnum(Fn, Fm)`Floating point (scalar)
fmaxnm	Vd.T, Vn.T, Vm.T	0 Q 0 01110 0 sz 1 Rm 11000 1 Rn Rd0x0E20C400 / mask 0xBFA0FC00	Maximum of floating point elements (a number wins against NaN)`for every element: Vd[i] = maxnum(Vn[i], Vm[i])`Vector (SIMD)
fmaxnmp	Vd.T, Vn.T, Vm.T	0 Q 1 01110 0 sz 1 Rm 11000 1 Rn Rd0x2E20C400 / mask 0xBFA0FC00	Maximum of adjacent floating point pairs (a number wins against NaN)`for every element: Vd[i] = maxnum of each pair of (Vn:Vm)`Vector (SIMD)
fmaxnmv	Sd, Vn.4S	0 1 1 01110 0 0 11000 01100 10 Rn Rd0x6E30C800 / mask 0xFFFFFC00	Maximum of all floating point elements (a number wins against NaN)`Sd = maxnum of all elements of Vn`Vector (SIMD)
fmaxp	Vd.T, Vn.T, Vm.T	0 Q 1 01110 0 sz 1 Rm 11110 1 Rn Rd0x2E20F400 / mask 0xBFA0FC00	Maximum of adjacent floating point pairs`for every element: Vd[i] = max of each pair of (Vn:Vm)`Vector (SIMD)
fmaxv	Sd, Vn.4S	0 1 1 01110 0 0 11000 01111 10 Rn Rd0x6E30F800 / mask 0xFFFFFC00	Maximum of all floating point elements`Sd = max of all elements of Vn`Vector (SIMD)
fmin	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 0101 10 Rn Rd0x1E205800 / mask 0xFF20FC00	Minimum (NaN propagates)`Fd = min(Fn, Fm)`Floating point (scalar)
fmin	Vd.T, Vn.T, Vm.T	0 Q 0 01110 1 sz 1 Rm 11110 1 Rn Rd0x0EA0F400 / mask 0xBFA0FC00	Minimum of floating point elements`for every element: Vd[i] = min(Vn[i], Vm[i])`Vector (SIMD)
fminnm	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 0111 10 Rn Rd0x1E207800 / mask 0xFF20FC00	Minimum (a number wins against NaN)`Fd = minnum(Fn, Fm)`Floating point (scalar)
fminnm	Vd.T, Vn.T, Vm.T	0 Q 0 01110 1 sz 1 Rm 11000 1 Rn Rd0x0EA0C400 / mask 0xBFA0FC00	Minimum of floating point elements (a number wins against NaN)`for every element: Vd[i] = minnum(Vn[i], Vm[i])`Vector (SIMD)
fminnmp	Vd.T, Vn.T, Vm.T	0 Q 1 01110 1 sz 1 Rm 11000 1 Rn Rd0x2EA0C400 / mask 0xBFA0FC00	Minimum of adjacent floating point pairs (a number wins against NaN)`for every element: Vd[i] = minnum of each pair of (Vn:Vm)`Vector (SIMD)
fminnmv	Sd, Vn.4S	0 1 1 01110 1 0 11000 01100 10 Rn Rd0x6EB0C800 / mask 0xFFFFFC00	Minimum of all floating point elements (a number wins against NaN)`Sd = minnum of all elements of Vn`Vector (SIMD)
fminp	Vd.T, Vn.T, Vm.T	0 Q 1 01110 1 sz 1 Rm 11110 1 Rn Rd0x2EA0F400 / mask 0xBFA0FC00	Minimum of adjacent floating point pairs`for every element: Vd[i] = min of each pair of (Vn:Vm)`Vector (SIMD)
fminv	Sd, Vn.4S	0 1 1 01110 1 0 11000 01111 10 Rn Rd0x6EB0F800 / mask 0xFFFFFC00	Minimum of all floating point elements`Sd = min of all elements of Vn`Vector (SIMD)
fmla	Vd.T, Vn.T, Vm.T	0 Q 0 01110 0 sz 1 Rm 11001 1 Rn Rd0x0E20CC00 / mask 0xBFA0FC00	Multiplication with addition to the destination (floating point)`for every element: Vd[i] = Vd[i] + Vn[i] * Vm[i]`Vector (SIMD)
fmla	Vd.T, Vn.T, Vm.Ts[index]	0 Q 0 01111 1 sz L M Rm 0001 H 0 Rn Rd0x0F801000 / mask 0xBF80F400	Floating point multiplication by an element, added to the destination`for every element: Vd[i] = Vd[i] + Vn[i] * Vm[index]`Vector (SIMD)
fmlal	Vd.2S, Vn.2H, Vm.2H	0 Q 0 01110 0 0 1 Rm 11101 1 Rn Rd0x0E20EC00 / mask 0xBFE0FC00	Multiplication of half-precision numbers with widening to single, added to the destination (low half)`for every element: Vd[i] = Vd[i] + float(Vn[i]) * float(Vm[i])`Vector (SIMD)
fmlal2	Vd.2S, Vn.2H, Vm.2H	0 Q 1 01110 0 0 1 Rm 11001 1 Rn Rd0x2E20CC00 / mask 0xBFE0FC00	Like fmlal, but with the high half of the sources`for every element: Vd[i] = Vd[i] + float(Vn[i + n]) * float(Vm[i + n])`Vector (SIMD)
fmls	Vd.T, Vn.T, Vm.T	0 Q 0 01110 1 sz 1 Rm 11001 1 Rn Rd0x0EA0CC00 / mask 0xBFA0FC00	Multiplication with subtraction from the destination (floating point)`for every element: Vd[i] = Vd[i] - Vn[i] * Vm[i]`Vector (SIMD)
fmls	Vd.T, Vn.T, Vm.Ts[index]	0 Q 0 01111 1 sz L M Rm 0101 H 0 Rn Rd0x0F805000 / mask 0xBF80F400	Floating point multiplication by an element, subtracted from the destination`for every element: Vd[i] = Vd[i] - Vn[i] * Vm[index]`Vector (SIMD)
fmlsl	Vd.2S, Vn.2H, Vm.2H	0 Q 0 01110 1 0 1 Rm 11101 1 Rn Rd0x0EA0EC00 / mask 0xBFE0FC00	Multiplication of half-precision numbers with widening to single, subtracted from the destination (low half)`for every element: Vd[i] = Vd[i] - float(Vn[i]) * float(Vm[i])`Vector (SIMD)
fmlsl2	Vd.2S, Vn.2H, Vm.2H	0 Q 1 01110 1 0 1 Rm 11001 1 Rn Rd0x2EA0CC00 / mask 0xBFE0FC00	Like fmlsl, but with the high half of the sources`for every element: Vd[i] = Vd[i] - float(Vn[i + n]) * float(Vm[i + n])`Vector (SIMD)
fmov	Fd, Fn	0 0 0 11110 ftype 1 000000 10000 Rn Rd0x1E204000 / mask 0xFF3FFC00	Copy of a floating point register`Fd = Fn`Floating point (scalar)
	Fd, #imm	0 0 0 11110 ftype 1 imm8 100 00000 Rd0x1E201000 / mask 0xFF201FE0	Load of a floating point constant (encoded in 8 bits: +-n/16 * 2^r)`Fd = expand_imm(imm8)`Floating point (scalar)
	Wd, Sn	0 0 0 11110 00 1 00 110 000000 Rn Rd0x1E260000 / mask 0xFFFFFC00	Bitwise copy of a single register to an integer register`Wd = bits(Sn)`Floating point (scalar)
	Sd, Wn	0 0 0 11110 00 1 00 111 000000 Rn Rd0x1E270000 / mask 0xFFFFFC00	Bitwise copy of an integer register to a single register`Sd = bits(Wn)`Floating point (scalar)
	Xd, Dn	1 0 0 11110 01 1 00 110 000000 Rn Rd0x9E660000 / mask 0xFFFFFC00	Bitwise copy of a double register to an integer register`Xd = bits(Dn)`Floating point (scalar)
	Dd, Xn	1 0 0 11110 01 1 00 111 000000 Rn Rd0x9E670000 / mask 0xFFFFFC00	Bitwise copy of an integer register to a double register`Dd = bits(Xn)`Floating point (scalar)
	Vd.T, #imm8{, lsl #amount}	0 Q 0 0111100000 abc 1111 01 defgh Rd0x0F00F400 / mask 0xBFF8FC00	Load of a floating point constant (single) into all elements`Vd = fp_const(imm8)`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 1 0111100000 abc 1111 01 defgh Rd0x2F00F400 / mask 0xBFF8FC00	Load of a floating point constant (double) into both halves`Vd = fp_const(imm8)`Vector (SIMD)
fmsub	Fd, Fn, Fm, Fa	0 0 0 11111 ftype 0 Rm 1 Ra Rn Rd0x1F008000 / mask 0xFF208000	Multiply and subtract (fused, Fa - Fn * Fm)`Fd = Fa - Fn * Fm`Floating point (scalar)
fmul	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 0000 10 Rn Rd0x1E200800 / mask 0xFF20FC00	Multiplication`Fd = Fn * Fm`Floating point (scalar)
	Vd.T, Vn.T, Vm.T	0 Q 1 01110 0 sz 1 Rm 11011 1 Rn Rd0x2E20DC00 / mask 0xBFA0FC00	Multiplication of floating point elements`for every element: Vd[i] = Vn[i] * Vm[i]`Vector (SIMD)
	Vd.T, Vn.T, Vm.Ts[index]	0 Q 0 01111 1 sz L M Rm 1001 H 0 Rn Rd0x0F809000 / mask 0xBF80F400	Floating point multiplication by an element`for every element: Vd[i] = Vn[i] * Vm[index]`Vector (SIMD)
fmulx	Vd.T, Vn.T, Vm.T	0 Q 0 01110 0 sz 1 Rm 11011 1 Rn Rd0x0E20DC00 / mask 0xBFA0FC00	Multiplication of floating point elements (0 times infinity gives 2)`for every element: Vd[i] = Vn[i] * Vm[i]`Vector (SIMD)
fmulx	Vd.T, Vn.T, Vm.Ts[index]	0 Q 1 01111 1 sz L M Rm 1001 H 0 Rn Rd0x2F809000 / mask 0xBF80F400	Floating point multiplication by an element (0 times infinity gives 2)`for every element: Vd[i] = Vn[i] * Vm[index]`Vector (SIMD)
fneg	Fd, Fn	0 0 0 11110 ftype 1 000010 10000 Rn Rd0x1E214000 / mask 0xFF3FFC00	Sign change`Fd = -Fn`Floating point (scalar)
fneg	Vd.T, Vn.T	0 Q 1 01110 1 sz 10000 01111 10 Rn Rd0x2EA0F800 / mask 0xBFBFFC00	Sign change of floating point elements`for every element: Vd[i] = -Vn[i]`Vector (SIMD)
fnmadd	Fd, Fn, Fm, Fa	0 0 0 11111 ftype 1 Rm 0 Ra Rn Rd0x1F200000 / mask 0xFF208000	Negated multiply and add (fused)`Fd = -Fa - Fn * Fm`Floating point (scalar)
fnmsub	Fd, Fn, Fm, Fa	0 0 0 11111 ftype 1 Rm 1 Ra Rn Rd0x1F208000 / mask 0xFF208000	Negated multiply and subtract (fused)`Fd = -Fa + Fn * Fm`Floating point (scalar)
fnmul	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 1000 10 Rn Rd0x1E208800 / mask 0xFF20FC00	Multiplication with sign change`Fd = -(Fn * Fm)`Floating point (scalar)
frecpe	Vd.T, Vn.T	0 Q 0 01110 1 sz 10000 11101 10 Rn Rd0x0EA1D800 / mask 0xBFBFFC00	Estimate of the reciprocal`for every element: Vd[i] = estimate(1 / Vn[i])`Vector (SIMD)
frecps	Vd.T, Vn.T, Vm.T	0 Q 0 01110 0 sz 1 Rm 11111 1 Rn Rd0x0E20FC00 / mask 0xBFA0FC00	Step of the Newton-Raphson iteration for the reciprocal`for every element: Vd[i] = 2 - Vn[i] * Vm[i]`Vector (SIMD)
frecpx	Fd, Fn	01 0 11110 1 sz 10000 11111 10 Rn Rd0x5EA1F800 / mask 0xFFBFFC00	Estimate of the reciprocal of an exponent (scalar)`Fd = reciprocal_exponent(Fn)`Floating point (scalar)
frint32x	Vd.T, Vn.T	0 Q 1 01110 0 sz 10000 11110 10 Rn Rd0x2E21E800 / mask 0xBFBFFC00	Rounding to an integer value that fits 32 bits (by the current rounding mode)`for every element: Vd[i] = round32(Vn[i])`Vector (SIMD)
frint32z	Vd.T, Vn.T	0 Q 0 01110 0 sz 10000 11110 10 Rn Rd0x0E21E800 / mask 0xBFBFFC00	Rounding to an integer value that fits 32 bits (toward zero)`for every element: Vd[i] = trunc32(Vn[i])`Vector (SIMD)
frint64x	Vd.T, Vn.T	0 Q 1 01110 0 sz 10000 11111 10 Rn Rd0x2E21F800 / mask 0xBFBFFC00	Rounding to an integer value that fits 64 bits (by the current rounding mode)`for every element: Vd[i] = round64(Vn[i])`Vector (SIMD)
frint64z	Vd.T, Vn.T	0 Q 0 01110 0 sz 10000 11111 10 Rn Rd0x0E21F800 / mask 0xBFBFFC00	Rounding to an integer value that fits 64 bits (toward zero)`for every element: Vd[i] = trunc64(Vn[i])`Vector (SIMD)
frinta	Fd, Fn	0 0 0 11110 ftype 1 001100 10000 Rn Rd0x1E264000 / mask 0xFF3FFC00	Rounding to an integer value (to nearest, ties away from zero)`Fd = round_half_away(Fn)`Floating point (scalar)
frinta	Vd.T, Vn.T	0 Q 1 01110 0 sz 10000 11000 10 Rn Rd0x2E218800 / mask 0xBFBFFC00	Rounding to an integer value (to nearest, ties away from zero)`for every element: Vd[i] = round_half_away(Vn[i])`Vector (SIMD)
frinti	Fd, Fn	0 0 0 11110 ftype 1 001111 10000 Rn Rd0x1E27C000 / mask 0xFF3FFC00	Rounding to an integer value (mode of the control register)`Fd = round(Fn)`Floating point (scalar)
frinti	Vd.T, Vn.T	0 Q 1 01110 1 sz 10000 11001 10 Rn Rd0x2EA19800 / mask 0xBFBFFC00	Rounding to an integer value (by the current rounding mode)`for every element: Vd[i] = round(Vn[i])`Vector (SIMD)
frintm	Fd, Fn	0 0 0 11110 ftype 1 001010 10000 Rn Rd0x1E254000 / mask 0xFF3FFC00	Rounding to an integer value (toward minus infinity)`Fd = floor(Fn)`Floating point (scalar)
frintm	Vd.T, Vn.T	0 Q 0 01110 0 sz 10000 11001 10 Rn Rd0x0E219800 / mask 0xBFBFFC00	Rounding to an integer value (toward minus infinity)`for every element: Vd[i] = floor(Vn[i])`Vector (SIMD)
frintn	Fd, Fn	0 0 0 11110 ftype 1 001000 10000 Rn Rd0x1E244000 / mask 0xFF3FFC00	Rounding to an integer value (to nearest, even on a tie)`Fd = round_to_nearest_even(Fn)`Floating point (scalar)
frintn	Vd.T, Vn.T	0 Q 0 01110 0 sz 10000 11000 10 Rn Rd0x0E218800 / mask 0xBFBFFC00	Rounding to an integer value (to nearest, even on a tie)`for every element: Vd[i] = round_to_nearest_even(Vn[i])`Vector (SIMD)
frintp	Fd, Fn	0 0 0 11110 ftype 1 001001 10000 Rn Rd0x1E24C000 / mask 0xFF3FFC00	Rounding to an integer value (toward plus infinity)`Fd = ceil(Fn)`Floating point (scalar)
frintp	Vd.T, Vn.T	0 Q 0 01110 1 sz 10000 11000 10 Rn Rd0x0EA18800 / mask 0xBFBFFC00	Rounding to an integer value (toward plus infinity)`for every element: Vd[i] = ceil(Vn[i])`Vector (SIMD)
frintx	Fd, Fn	0 0 0 11110 ftype 1 001110 10000 Rn Rd0x1E274000 / mask 0xFF3FFC00	Rounding to an integer value (mode of the control register, signals inexact)`Fd = round(Fn)`Floating point (scalar)
frintx	Vd.T, Vn.T	0 Q 1 01110 0 sz 10000 11001 10 Rn Rd0x2E219800 / mask 0xBFBFFC00	Rounding to an integer value (by the current rounding mode, raising an inexact exception)`for every element: Vd[i] = round(Vn[i])`Vector (SIMD)
frintz	Fd, Fn	0 0 0 11110 ftype 1 001011 10000 Rn Rd0x1E25C000 / mask 0xFF3FFC00	Rounding to an integer value (toward zero)`Fd = trunc(Fn)`Floating point (scalar)
frintz	Vd.T, Vn.T	0 Q 0 01110 1 sz 10000 11001 10 Rn Rd0x0EA19800 / mask 0xBFBFFC00	Rounding to an integer value (toward zero)`for every element: Vd[i] = trunc(Vn[i])`Vector (SIMD)
frsqrte	Vd.T, Vn.T	0 Q 1 01110 1 sz 10000 11101 10 Rn Rd0x2EA1D800 / mask 0xBFBFFC00	Estimate of the reciprocal square root`for every element: Vd[i] = estimate(1 / sqrt(Vn[i]))`Vector (SIMD)
frsqrts	Vd.T, Vn.T, Vm.T	0 Q 0 01110 1 sz 1 Rm 11111 1 Rn Rd0x0EA0FC00 / mask 0xBFA0FC00	Step of the Newton-Raphson iteration for the reciprocal square root`for every element: Vd[i] = (3 - Vn[i] * Vm[i]) / 2`Vector (SIMD)
fsqrt	Fd, Fn	0 0 0 11110 ftype 1 000011 10000 Rn Rd0x1E21C000 / mask 0xFF3FFC00	Square root`Fd = sqrt(Fn)`Floating point (scalar)
fsqrt	Vd.T, Vn.T	0 Q 1 01110 1 sz 10000 11111 10 Rn Rd0x2EA1F800 / mask 0xBFBFFC00	Square root of floating point elements`for every element: Vd[i] = sqrt(Vn[i])`Vector (SIMD)
fsub	Fd, Fn, Fm	0 0 0 11110 ftype 1 Rm 0011 10 Rn Rd0x1E203800 / mask 0xFF20FC00	Subtraction`Fd = Fn - Fm`Floating point (scalar)
fsub	Vd.T, Vn.T, Vm.T	0 Q 0 01110 1 sz 1 Rm 11010 1 Rn Rd0x0EA0D400 / mask 0xBFA0FC00	Subtraction of floating point elements`for every element: Vd[i] = Vn[i] - Vm[i]`Vector (SIMD)
gmi	Xd, Xn\|SP, Xm	1 0 0 11010110 Rm 000101 Rn Rd0x9AC01400 / mask 0xFFE0FC00	Insertion of a tag into an exclude mask`Xd = Xm \| (1 << tag of Xn)`Memory tagging (MTE)
hint	#imm7also shown as: nop, yield, wfe, wfi, sev, sevl, bti, csdb, esb, psb, tsb	1101010100 0 00 011 0010 CRm op2 111110xD503201F / mask 0xFFFFF01F	Hint to the processor (nop, yield, wfe, wfi, sev, bti ...)`no change of the program (a hint)`System and privileged
hlt	#imm16	11010100 010 imm16 000 000xD4400000 / mask 0xFFE0001F	Halt for a debugger`enter debug state`System and privileged
hvc	#imm16	11010100 000 imm16 000 100xD4000002 / mask 0xFFE0001F	Hypervisor call (exception level 2)`raise a hypervisor call exception`System and privileged
ins	Vd.Ts[index], Rnalso shown as: mov	0 1 0 01110000 imm5 0 0011 1 Rn Rd0x4E001C00 / mask 0xFFE0FC00	Insertion of an integer register into one element`Vd[index] = Rn`Vector (SIMD)
irg	Xd\|SP, Xn\|SP{, Xm}	1 0 0 11010110 Rm 000100 Rn Rd0x9AC01000 / mask 0xFFE0FC00	Insertion of a random tag into an address`Xd = Xn with a random tag (not in the exclude mask Xm)`Memory tagging (MTE)
isb	{#imm4}	1101010100 0 00 011 0011 CRm 1 10 111110xD50330DF / mask 0xFFFFF0FF	Instruction barrier: flushes the pipeline`all instructions after it are fetched anew`System and privileged
ld1	{Vt.T}, [Xn\|SP]	0 Q 0011000 1 000000 0111 size Rn Rt0x0C407000 / mask 0xBFFFF000	Load of one vector register from memory`Vt = [Rn]`Vector (SIMD)
	{Vt.T, Vt2.T}, [Xn\|SP]	0 Q 0011000 1 000000 1010 size Rn Rt0x0C40A000 / mask 0xBFFFF000	Load of 2 registers from memory`registers = [Rn] (2 registers)`Vector (SIMD)
	{Vt.T, Vt2.T, Vt3.T}, [Xn\|SP]	0 Q 0011000 1 000000 0110 size Rn Rt0x0C406000 / mask 0xBFFFF000	Load of 3 registers from memory`registers = [Rn] (3 registers)`Vector (SIMD)
	{Vt.T, Vt2.T, Vt3.T, Vt4.T}, [Xn\|SP]	0 Q 0011000 1 000000 0010 size Rn Rt0x0C402000 / mask 0xBFFFF000	Load of 4 registers from memory`registers = [Rn] (4 registers)`Vector (SIMD)
	{Vt.Ts}[index], [Xn\|SP]	0 Q 0011010 1 0 00000 e 0 S size Rn Rt0x0D400000 / mask 0xBFFF2000	Load of one element (lane) (one register)`Vt[index] = [Rn]`Vector (SIMD)
ld1r	{Vt.T}, [Xn\|SP]	0 Q 0011010 1 0 00000 110 0 size Rn Rt0x0D40C000 / mask 0xBFFFF000	Load of one element from memory into all elements of 1 registers (replicate)`every element of every register = [Rn]`Vector (SIMD)
ld2	{Vt.T, Vt2.T}, [Xn\|SP]	0 Q 0011000 1 000000 1000 size Rn Rt0x0C408000 / mask 0xBFFFF000	Load of 2 registers (elements interleaved) from memory`registers = [Rn] (2 registers (elements interleaved))`Vector (SIMD)
	{Vt.T, Vt2.T}, [Xn\|SP], Xm\|#imm	0 Q 0011001 1 0 Rm 1000 size Rn Rt0x0CC08000 / mask 0xBFE0F000	Load of 2 registers (elements interleaved) with post-indexing`registers = [Rn]; Rn = Rn + Xm or the size`Vector (SIMD)
	{Vt.Ts, Vt2.Ts}[index], [Xn\|SP]	0 Q 0011010 1 1 00000 e 0 S size Rn Rt0x0D600000 / mask 0xBFFF2000	Load of one element (lane) of 2 registers`Vt[index] = [Rn]`Vector (SIMD)
ld2r	{Vt.T, Vt2.T}, [Xn\|SP]	0 Q 0011010 1 1 00000 110 0 size Rn Rt0x0D60C000 / mask 0xBFFFF000	Load of one element from memory into all elements of 2 registers (replicate)`every element of every register = [Rn]`Vector (SIMD)
ld3	{Vt.T, Vt2.T, Vt3.T}, [Xn\|SP]	0 Q 0011000 1 000000 0100 size Rn Rt0x0C404000 / mask 0xBFFFF000	Load of 3 registers (elements interleaved) from memory`registers = [Rn] (3 registers (elements interleaved))`Vector (SIMD)
	{Vt.T, Vt2.T, Vt3.T}, [Xn\|SP], Xm\|#imm	0 Q 0011001 1 0 Rm 0100 size Rn Rt0x0CC04000 / mask 0xBFE0F000	Load of 3 registers (elements interleaved) with post-indexing`registers = [Rn]; Rn = Rn + Xm or the size`Vector (SIMD)
	{Vt.Ts, Vt2.Ts, Vt3.Ts}[index], [Xn\|SP]	0 Q 0011010 1 0 00000 e 1 S size Rn Rt0x0D402000 / mask 0xBFFF2000	Load of one element (lane) of 3 registers`Vt[index] = [Rn]`Vector (SIMD)
ld3r	{Vt.T, Vt2.T, Vt3.T}, [Xn\|SP]	0 Q 0011010 1 0 00000 111 0 size Rn Rt0x0D40E000 / mask 0xBFFFF000	Load of one element from memory into all elements of 3 registers (replicate)`every element of every register = [Rn]`Vector (SIMD)
ld4	{Vt.T, Vt2.T, Vt3.T, Vt4.T}, [Xn\|SP]	0 Q 0011000 1 000000 0000 size Rn Rt0x0C400000 / mask 0xBFFFF000	Load of 4 registers (elements interleaved) from memory`registers = [Rn] (4 registers (elements interleaved))`Vector (SIMD)
	{Vt.T, Vt2.T, Vt3.T, Vt4.T}, [Xn\|SP], Xm\|#imm	0 Q 0011001 1 0 Rm 0000 size Rn Rt0x0CC00000 / mask 0xBFE0F000	Load of 4 registers (elements interleaved) with post-indexing`registers = [Rn]; Rn = Rn + Xm or the size`Vector (SIMD)
	{Vt.Ts, Vt2.Ts, Vt3.Ts, Vt4.Ts}[index], [Xn\|SP]	0 Q 0011010 1 1 00000 e 1 S size Rn Rt0x0D602000 / mask 0xBFFF2000	Load of one element (lane) of 4 registers`Vt[index] = [Rn]`Vector (SIMD)
ld4r	{Vt.T, Vt2.T, Vt3.T, Vt4.T}, [Xn\|SP]	0 Q 0011010 1 1 00000 111 0 size Rn Rt0x0D60E000 / mask 0xBFFFF000	Load of one element from memory into all elements of 4 registers (replicate)`every element of every register = [Rn]`Vector (SIMD)
ldadd	Ws, Wt, [Xn\|SP]also shown as: ldadda, ldaddal, ldaddl, ldaddb, ldaddab, ldaddalb, ldaddlb, ldaddh, ldaddah, ldaddalh, ldaddlh, staddb, staddh, stadd, staddl, staddlb, staddlh	size 111 0 00 A R 1 Rs 0 000 00 Rn Rt0x38200000 / mask 0x3F20FC00	Atomic memory operation: Addition of the memory value and a register, the old value goes to the destination register (variants: b = byte, h = half word, a = acquire, l = release, st... without a destination register)`t = [Rn]; [Rn] = t + Ws; Wt = t`Atomic memory operations (LSE)
ldapr	Wt, [Xn\|SP]also shown as: ldaprb, ldaprh	size 111 0 00 1 0 1 11111 1 100 00 Rn Rt0x38BFC000 / mask 0x3FFFFC00	Load with release consistency (acquire for earlier accesses only, RCpc variant; b = byte, h = half word)`Wt = [Rn]`Loads and stores
ldapur	Wt, [Xn\|SP{, #imm9}]also shown as: ldapurb, ldapurh	size 011 001 01 0 imm9 00 Rn Rt0x19400000 / mask 0x3FE00C00	Load with acquire (RCpc, unscaled, address: Rn + imm9; b = byte, h = half word)`Wt = [Rn + imm9]`Loads and stores
ldapursb	Xt, [Xn\|SP{, #imm9}]also shown as: ldapursh, ldapursw	size 011 001 10 0 imm9 00 Rn Rt0x19800000 / mask 0x3FE00C00	Load with acquire (RCpc), sign-extended to 64 bit (b = byte, h = half word, w = word)`Xt = sext([Rn + imm9])`Loads and stores
ldar	Wt, [Xn\|SP]	10 001000 1 1 0 11111 1 11111 Rn Rt0x88DFFC00 / mask 0xFFFFFC00	Load with acquire (word)`Rt = [Rn]; acquire`Loads and stores
ldar	Xt, [Xn\|SP]	11 001000 1 1 0 11111 1 11111 Rn Rt0xC8DFFC00 / mask 0xFFFFFC00	Load with acquire (double word)`Rt = [Rn]; acquire`Loads and stores
ldarb	Wt, [Xn\|SP]	00 001000 1 1 0 11111 1 11111 Rn Rt0x08DFFC00 / mask 0xFFFFFC00	Load with acquire (byte)`Rt = [Rn]; acquire`Loads and stores
ldarh	Wt, [Xn\|SP]	01 001000 1 1 0 11111 1 11111 Rn Rt0x48DFFC00 / mask 0xFFFFFC00	Load with acquire (half word)`Rt = [Rn]; acquire`Loads and stores
ldaxp	Rt, Rt2, [Xn\|SP]	1 sz 001000 0 1 1 11111 1 Rt2 Rn Rt0x887F8000 / mask 0xBFFF8000	Load of a register pair (exclusive) with acquire`Rt = [Rn]; Rt2 = [Rn + size]; acquire; set the exclusive monitor`Loads and stores
ldaxr	Wt, [Xn\|SP]	10 001000 0 1 0 11111 1 11111 Rn Rt0x885FFC00 / mask 0xFFFFFC00	Load-exclusive with acquire (word)`Rt = [Rn]; acquire; set the exclusive monitor`Loads and stores
ldaxr	Xt, [Xn\|SP]	11 001000 0 1 0 11111 1 11111 Rn Rt0xC85FFC00 / mask 0xFFFFFC00	Load-exclusive with acquire (double word)`Rt = [Rn]; acquire; set the exclusive monitor`Loads and stores
ldaxrb	Wt, [Xn\|SP]	00 001000 0 1 0 11111 1 11111 Rn Rt0x085FFC00 / mask 0xFFFFFC00	Load-exclusive with acquire (byte)`Rt = [Rn]; acquire; set the exclusive monitor`Loads and stores
ldaxrh	Wt, [Xn\|SP]	01 001000 0 1 0 11111 1 11111 Rn Rt0x485FFC00 / mask 0xFFFFFC00	Load-exclusive with acquire (half word)`Rt = [Rn]; acquire; set the exclusive monitor`Loads and stores
ldclr	Ws, Wt, [Xn\|SP]also shown as: ldclra, ldclral, ldclrl, ldclrb, ldclrab, ldclralb, ldclrlb, ldclrh, ldclrah, ldclralh, ldclrlh, stclrb, stclrh, stclr, stclrl, stclrlb, stclrlh	size 111 0 00 A R 1 Rs 0 001 00 Rn Rt0x38201000 / mask 0x3F20FC00	Atomic memory operation: Clearing of bits (AND with the inverted operand) of the memory value and a register, the old value goes to the destination register (variants: b = byte, h = half word, a = acquire, l = release, st... without a destination register)`t = [Rn]; [Rn] = t & ~Ws; Wt = t`Atomic memory operations (LSE)
ldeor	Ws, Wt, [Xn\|SP]also shown as: ldeora, ldeoral, ldeorl, ldeorb, ldeorab, ldeoralb, ldeorlb, ldeorh, ldeorah, ldeoralh, ldeorlh, steorb, steorh, steor, steorl, steorlb, steorlh	size 111 0 00 A R 1 Rs 0 010 00 Rn Rt0x38202000 / mask 0x3F20FC00	Atomic memory operation: exclusive OR of the memory value and a register, the old value goes to the destination register (variants: b = byte, h = half word, a = acquire, l = release, st... without a destination register)`t = [Rn]; [Rn] = t ^ Ws; Wt = t`Atomic memory operations (LSE)
ldg	Xt, [Xn\|SP{, #imm9}]	11011001 011 imm9 00 Rn Rt0xD9600000 / mask 0xFFE00C00	Load of the tag from memory into an address`Xt = Xt with tag of [Rn + imm9 * 16]`Memory tagging (MTE)
ldlar	Wt, [Xn\|SP]also shown as: ldlarb, ldlarh	size 001000 1 1 0 11111 0 11111 Rn Rt0x08DF7C00 / mask 0x3FFFFC00	Load with acquire for an ordered memory region (LORegion; b = byte, h = half word)`Wt = [Rn]`Loads and stores
ldnp	Rt, Rt2, [Xn\|SP{, #imm7}]	sf 0 101 0 000 1 imm7 Rt2 Rn Rt0x28400000 / mask 0x7FC00000	Load of a register pair with a non-temporal hint`Rt = [addr]; Rt2 = [addr + size]`Loads and stores
ldp	Rt, Rt2, [Xn\|SP], #imm7	sf 0 101 0 001 1 imm7 Rt2 Rn Rt0x28C00000 / mask 0x7FC00000	Load of a register pair (post-indexed)`Rt = [addr]; Rt2 = [addr + size]; addr = Rn; Rn = Rn + imm7 * size`Loads and stores
	Rt, Rt2, [Xn\|SP{, #imm7}]	sf 0 101 0 010 1 imm7 Rt2 Rn Rt0x29400000 / mask 0x7FC00000	Load of a register pair`Rt = [addr]; Rt2 = [addr + size]; addr = Rn + imm7 * size`Loads and stores
	Rt, Rt2, [Xn\|SP, #imm7]!	sf 0 101 0 011 1 imm7 Rt2 Rn Rt0x29C00000 / mask 0x7FC00000	Load of a register pair (pre-indexed)`Rt = [addr]; Rt2 = [addr + size]; Rn = Rn + imm7 * size; addr = Rn`Loads and stores
	Ft, Ft2, [Xn\|SP{, #imm7}]	opc 101 1 010 1 imm7 Rt2 Rn Rt0x2D400000 / mask 0x3FC00000	Load of a pair of floating point / vector registers (opc 00 = S, 01 = D, 10 = Q)`Ft = [addr]; Ft2 = [addr + size]`Loads and stores
ldpsw	Xt, Xt2, [Xn\|SP], #imm7	01 101 0 001 1 imm7 Rt2 Rn Rt0x68C00000 / mask 0xFFC00000	Load of a pair of signed words (post-indexed)`Xt = sext([addr]); Xt2 = sext([addr + 4]); addr = Rn; Rn = Rn + imm7 * 4`Loads and stores
	Xt, Xt2, [Xn\|SP{, #imm7}]	01 101 0 010 1 imm7 Rt2 Rn Rt0x69400000 / mask 0xFFC00000	Load of a pair of signed words`Xt = sext([addr]); Xt2 = sext([addr + 4]); addr = Rn + imm7 * 4`Loads and stores
	Xt, Xt2, [Xn\|SP, #imm7]!	01 101 0 011 1 imm7 Rt2 Rn Rt0x69C00000 / mask 0xFFC00000	Load of a pair of signed words (pre-indexed)`Xt = sext([addr]); Xt2 = sext([addr + 4]); Rn = Rn + imm7 * 4; addr = Rn`Loads and stores
ldr	Wt, [Xn\|SP{, #imm12}]	10 111 0 01 01 imm12 Rn Rt0xB9400000 / mask 0xFFC00000	Load of a word (32 bit) (address: Rn + imm12 * size)`Wt = [addr]; addr = Rn + imm12 * size`Loads and stores
	Wt, [Xn\|SP, #imm9]!	10 111 0 00 01 0 imm9 11 Rn Rt0xB8400C00 / mask 0xFFE00C00	Load of a word (32 bit) (pre-indexed: Rn is changed first)`Wt = [addr]; Rn = Rn + imm9; addr = Rn`Loads and stores
	Wt, [Xn\|SP], #imm9	10 111 0 00 01 0 imm9 01 Rn Rt0xB8400400 / mask 0xFFE00C00	Load of a word (32 bit) (post-indexed: Rn is changed afterwards)`Wt = [addr]; addr = Rn; Rn = Rn + imm9`Loads and stores
	Wt, [Xn\|SP, Rm{, extend {#amount}}]	10 111 0 00 01 1 Rm option S 10 Rn Rt0xB8600800 / mask 0xFFE00C00	Load of a word (32 bit) (address: Rn + register, extended and shifted)`Wt = [addr]; addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
	Xt, [Xn\|SP{, #imm12}]	11 111 0 01 01 imm12 Rn Rt0xF9400000 / mask 0xFFC00000	Load of a double word (64 bit) (address: Rn + imm12 * size)`Xt = [addr]; addr = Rn + imm12 * size`Loads and stores
	Xt, [Xn\|SP, #imm9]!	11 111 0 00 01 0 imm9 11 Rn Rt0xF8400C00 / mask 0xFFE00C00	Load of a double word (64 bit) (pre-indexed: Rn is changed first)`Xt = [addr]; Rn = Rn + imm9; addr = Rn`Loads and stores
	Xt, [Xn\|SP], #imm9	11 111 0 00 01 0 imm9 01 Rn Rt0xF8400400 / mask 0xFFE00C00	Load of a double word (64 bit) (post-indexed: Rn is changed afterwards)`Xt = [addr]; addr = Rn; Rn = Rn + imm9`Loads and stores
	Xt, [Xn\|SP, Rm{, extend {#amount}}]	11 111 0 00 01 1 Rm option S 10 Rn Rt0xF8600800 / mask 0xFFE00C00	Load of a double word (64 bit) (address: Rn + register, extended and shifted)`Xt = [addr]; addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
	Wt, label	00 011 0 00 imm19 Rt0x18000000 / mask 0xFF000000	Load of a word relative to the program counter (+-1 MB)`Wt = [pc + sext(imm19 << 2)]`Loads and stores
	Xt, label	01 011 0 00 imm19 Rt0x58000000 / mask 0xFF000000	Load of a double word relative to the program counter (+-1 MB)`Xt = [pc + sext(imm19 << 2)]`Loads and stores
	Ft, [Xn\|SP{, #imm12}]	1 x 111 1 01 01 imm12 Rn Rt0xBD400000 / mask 0xBFC00000	Load of a single (x=0) or double (x=1) register`Ft = [Rn + imm12 * size]`Loads and stores
	Qt, [Xn\|SP{, #imm12}]	00 111 1 01 11 imm12 Rn Rt0x3DC00000 / mask 0xFFC00000	Load of a 128-bit vector register`Qt = [Rn + imm12 * 16]`Loads and stores
ldraa	Xt, [Xn\|SP{, #simm10}]also shown as: ldrab	11 111 0 00 M S 1 imm9 W 1 Rn Rt0xF8200400 / mask 0xFF200400	Load with an authenticated base address (a = key A, b = key B; optionally pre-indexed)`Xt = [aut(Xn, key, 0) + simm10 * 8]`Pointer authentication (PAC)
ldrb	Wt, [Xn\|SP{, #imm12}]	00 111 0 01 01 imm12 Rn Rt0x39400000 / mask 0xFFC00000	Load of a byte (zero-extended) (address: Rn + imm12 * size)`Wt = zext([addr]); addr = Rn + imm12 * size`Loads and stores
	Wt, [Xn\|SP, #imm9]!	00 111 0 00 01 0 imm9 11 Rn Rt0x38400C00 / mask 0xFFE00C00	Load of a byte (zero-extended) (pre-indexed: Rn is changed first)`Wt = zext([addr]); Rn = Rn + imm9; addr = Rn`Loads and stores
	Wt, [Xn\|SP], #imm9	00 111 0 00 01 0 imm9 01 Rn Rt0x38400400 / mask 0xFFE00C00	Load of a byte (zero-extended) (post-indexed: Rn is changed afterwards)`Wt = zext([addr]); addr = Rn; Rn = Rn + imm9`Loads and stores
	Wt, [Xn\|SP, Rm{, extend {#amount}}]	00 111 0 00 01 1 Rm option S 10 Rn Rt0x38600800 / mask 0xFFE00C00	Load of a byte (zero-extended) (address: Rn + register, extended and shifted)`Wt = zext([addr]); addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
ldrh	Wt, [Xn\|SP{, #imm12}]	01 111 0 01 01 imm12 Rn Rt0x79400000 / mask 0xFFC00000	Load of a half word (zero-extended) (address: Rn + imm12 * size)`Wt = zext([addr]); addr = Rn + imm12 * size`Loads and stores
	Wt, [Xn\|SP, #imm9]!	01 111 0 00 01 0 imm9 11 Rn Rt0x78400C00 / mask 0xFFE00C00	Load of a half word (zero-extended) (pre-indexed: Rn is changed first)`Wt = zext([addr]); Rn = Rn + imm9; addr = Rn`Loads and stores
	Wt, [Xn\|SP], #imm9	01 111 0 00 01 0 imm9 01 Rn Rt0x78400400 / mask 0xFFE00C00	Load of a half word (zero-extended) (post-indexed: Rn is changed afterwards)`Wt = zext([addr]); addr = Rn; Rn = Rn + imm9`Loads and stores
	Wt, [Xn\|SP, Rm{, extend {#amount}}]	01 111 0 00 01 1 Rm option S 10 Rn Rt0x78600800 / mask 0xFFE00C00	Load of a half word (zero-extended) (address: Rn + register, extended and shifted)`Wt = zext([addr]); addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
ldrsb	Xt, [Xn\|SP{, #imm12}]	00 111 0 01 10 imm12 Rn Rt0x39800000 / mask 0xFFC00000	Load of a byte (sign-extended to 64 bit) (address: Rn + imm12 * size)`Xt = sext([addr]); addr = Rn + imm12 * size`Loads and stores
	Xt, [Xn\|SP, #imm9]!	00 111 0 00 10 0 imm9 11 Rn Rt0x38800C00 / mask 0xFFE00C00	Load of a byte (sign-extended to 64 bit) (pre-indexed: Rn is changed first)`Xt = sext([addr]); Rn = Rn + imm9; addr = Rn`Loads and stores
	Xt, [Xn\|SP], #imm9	00 111 0 00 10 0 imm9 01 Rn Rt0x38800400 / mask 0xFFE00C00	Load of a byte (sign-extended to 64 bit) (post-indexed: Rn is changed afterwards)`Xt = sext([addr]); addr = Rn; Rn = Rn + imm9`Loads and stores
	Xt, [Xn\|SP, Rm{, extend {#amount}}]	00 111 0 00 10 1 Rm option S 10 Rn Rt0x38A00800 / mask 0xFFE00C00	Load of a byte (sign-extended to 64 bit) (address: Rn + register, extended and shifted)`Xt = sext([addr]); addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
	Wt, [Xn\|SP{, #imm12}]	00 111 0 01 11 imm12 Rn Rt0x39C00000 / mask 0xFFC00000	Load of a byte (sign-extended to 32 bit) (address: Rn + imm12 * size)`Wt = sext([addr]); addr = Rn + imm12 * size`Loads and stores
	Wt, [Xn\|SP, #imm9]!	00 111 0 00 11 0 imm9 11 Rn Rt0x38C00C00 / mask 0xFFE00C00	Load of a byte (sign-extended to 32 bit) (pre-indexed: Rn is changed first)`Wt = sext([addr]); Rn = Rn + imm9; addr = Rn`Loads and stores
	Wt, [Xn\|SP], #imm9	00 111 0 00 11 0 imm9 01 Rn Rt0x38C00400 / mask 0xFFE00C00	Load of a byte (sign-extended to 32 bit) (post-indexed: Rn is changed afterwards)`Wt = sext([addr]); addr = Rn; Rn = Rn + imm9`Loads and stores
	Wt, [Xn\|SP, Rm{, extend {#amount}}]	00 111 0 00 11 1 Rm option S 10 Rn Rt0x38E00800 / mask 0xFFE00C00	Load of a byte (sign-extended to 32 bit) (address: Rn + register, extended and shifted)`Wt = sext([addr]); addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
ldrsh	Xt, [Xn\|SP{, #imm12}]	01 111 0 01 10 imm12 Rn Rt0x79800000 / mask 0xFFC00000	Load of a half word (sign-extended to 64 bit) (address: Rn + imm12 * size)`Xt = sext([addr]); addr = Rn + imm12 * size`Loads and stores
	Xt, [Xn\|SP, #imm9]!	01 111 0 00 10 0 imm9 11 Rn Rt0x78800C00 / mask 0xFFE00C00	Load of a half word (sign-extended to 64 bit) (pre-indexed: Rn is changed first)`Xt = sext([addr]); Rn = Rn + imm9; addr = Rn`Loads and stores
	Xt, [Xn\|SP], #imm9	01 111 0 00 10 0 imm9 01 Rn Rt0x78800400 / mask 0xFFE00C00	Load of a half word (sign-extended to 64 bit) (post-indexed: Rn is changed afterwards)`Xt = sext([addr]); addr = Rn; Rn = Rn + imm9`Loads and stores
	Xt, [Xn\|SP, Rm{, extend {#amount}}]	01 111 0 00 10 1 Rm option S 10 Rn Rt0x78A00800 / mask 0xFFE00C00	Load of a half word (sign-extended to 64 bit) (address: Rn + register, extended and shifted)`Xt = sext([addr]); addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
	Wt, [Xn\|SP{, #imm12}]	01 111 0 01 11 imm12 Rn Rt0x79C00000 / mask 0xFFC00000	Load of a half word (sign-extended to 32 bit) (address: Rn + imm12 * size)`Wt = sext([addr]); addr = Rn + imm12 * size`Loads and stores
	Wt, [Xn\|SP, #imm9]!	01 111 0 00 11 0 imm9 11 Rn Rt0x78C00C00 / mask 0xFFE00C00	Load of a half word (sign-extended to 32 bit) (pre-indexed: Rn is changed first)`Wt = sext([addr]); Rn = Rn + imm9; addr = Rn`Loads and stores
	Wt, [Xn\|SP], #imm9	01 111 0 00 11 0 imm9 01 Rn Rt0x78C00400 / mask 0xFFE00C00	Load of a half word (sign-extended to 32 bit) (post-indexed: Rn is changed afterwards)`Wt = sext([addr]); addr = Rn; Rn = Rn + imm9`Loads and stores
	Wt, [Xn\|SP, Rm{, extend {#amount}}]	01 111 0 00 11 1 Rm option S 10 Rn Rt0x78E00800 / mask 0xFFE00C00	Load of a half word (sign-extended to 32 bit) (address: Rn + register, extended and shifted)`Wt = sext([addr]); addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
ldrsw	Xt, [Xn\|SP{, #imm12}]	10 111 0 01 10 imm12 Rn Rt0xB9800000 / mask 0xFFC00000	Load of a word (sign-extended to 64 bit) (address: Rn + imm12 * size)`Xt = sext([addr]); addr = Rn + imm12 * size`Loads and stores
	Xt, [Xn\|SP, #imm9]!	10 111 0 00 10 0 imm9 11 Rn Rt0xB8800C00 / mask 0xFFE00C00	Load of a word (sign-extended to 64 bit) (pre-indexed: Rn is changed first)`Xt = sext([addr]); Rn = Rn + imm9; addr = Rn`Loads and stores
	Xt, [Xn\|SP], #imm9	10 111 0 00 10 0 imm9 01 Rn Rt0xB8800400 / mask 0xFFE00C00	Load of a word (sign-extended to 64 bit) (post-indexed: Rn is changed afterwards)`Xt = sext([addr]); addr = Rn; Rn = Rn + imm9`Loads and stores
	Xt, [Xn\|SP, Rm{, extend {#amount}}]	10 111 0 00 10 1 Rm option S 10 Rn Rt0xB8A00800 / mask 0xFFE00C00	Load of a word (sign-extended to 64 bit) (address: Rn + register, extended and shifted)`Xt = sext([addr]); addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
	Xt, label	10 011 0 00 imm19 Rt0x98000000 / mask 0xFF000000	Load of a signed word relative to the program counter (+-1 MB)`Xt = sext([pc + sext(imm19 << 2)])`Loads and stores
ldset	Ws, Wt, [Xn\|SP]also shown as: ldseta, ldsetal, ldsetl, ldsetb, ldsetab, ldsetalb, ldsetlb, ldseth, ldsetah, ldsetalh, ldsetlh, stsetb, stseth, stset, stsetl, stsetlb, stsetlh	size 111 0 00 A R 1 Rs 0 011 00 Rn Rt0x38203000 / mask 0x3F20FC00	Atomic memory operation: Setting of bits (OR) of the memory value and a register, the old value goes to the destination register (variants: b = byte, h = half word, a = acquire, l = release, st... without a destination register)`t = [Rn]; [Rn] = t \| Ws; Wt = t`Atomic memory operations (LSE)
ldsmax	Ws, Wt, [Xn\|SP]also shown as: ldsmaxa, ldsmaxal, ldsmaxl, ldsmaxb, ldsmaxab, ldsmaxalb, ldsmaxlb, ldsmaxh, ldsmaxah, ldsmaxalh, ldsmaxlh, stsmaxb, stsmaxh, stsmax, stsmaxl, stsmaxlb, stsmaxlh	size 111 0 00 A R 1 Rs 0 100 00 Rn Rt0x38204000 / mask 0x3F20FC00	Atomic memory operation: Maximum (signed) of the memory value and a register, the old value goes to the destination register (variants: b = byte, h = half word, a = acquire, l = release, st... without a destination register)`t = [Rn]; [Rn] = max_signed(t, Ws); Wt = t`Atomic memory operations (LSE)
ldsmin	Ws, Wt, [Xn\|SP]also shown as: ldsmina, ldsminal, ldsminl, ldsminb, ldsminab, ldsminalb, ldsminlb, ldsminh, ldsminah, ldsminalh, ldsminlh, stsminb, stsminh, stsmin, stsminl, stsminlb, stsminlh	size 111 0 00 A R 1 Rs 0 101 00 Rn Rt0x38205000 / mask 0x3F20FC00	Atomic memory operation: Minimum (signed) of the memory value and a register, the old value goes to the destination register (variants: b = byte, h = half word, a = acquire, l = release, st... without a destination register)`t = [Rn]; [Rn] = min_signed(t, Ws); Wt = t`Atomic memory operations (LSE)
ldtr	Wt, [Xn\|SP{, #imm9}]also shown as: ldtrb, ldtrh	size 111 0 00 01 0 imm9 10 Rn Rt0x38400800 / mask 0x3FE00C00	Load with the rights of user mode (unprivileged; b = byte, h = half word)`Wt = [Rn + imm9]`Loads and stores
ldtrsb	Xt, [Xn\|SP{, #imm9}]also shown as: ldtrsh, ldtrsw	size 111 0 00 10 0 imm9 10 Rn Rt0x38800800 / mask 0x3FE00C00	Load with the rights of user mode, sign-extended to 64 bit (b = byte, h = half word, w = word)`Xt = sext([Rn + imm9])`Loads and stores
ldumax	Ws, Wt, [Xn\|SP]also shown as: ldumaxa, ldumaxal, ldumaxl, ldumaxb, ldumaxab, ldumaxalb, ldumaxlb, ldumaxh, ldumaxah, ldumaxalh, ldumaxlh, stumaxb, stumaxh, stumax, stumaxl, stumaxlb, stumaxlh	size 111 0 00 A R 1 Rs 0 110 00 Rn Rt0x38206000 / mask 0x3F20FC00	Atomic memory operation: Maximum (unsigned) of the memory value and a register, the old value goes to the destination register (variants: b = byte, h = half word, a = acquire, l = release, st... without a destination register)`t = [Rn]; [Rn] = max_unsigned(t, Ws); Wt = t`Atomic memory operations (LSE)
ldumin	Ws, Wt, [Xn\|SP]also shown as: ldumina, lduminal, lduminl, lduminb, lduminab, lduminalb, lduminlb, lduminh, lduminah, lduminalh, lduminlh, stuminb, stuminh, stumin, stuminl, stuminlb, stuminlh	size 111 0 00 A R 1 Rs 0 111 00 Rn Rt0x38207000 / mask 0x3F20FC00	Atomic memory operation: Minimum (unsigned) of the memory value and a register, the old value goes to the destination register (variants: b = byte, h = half word, a = acquire, l = release, st... without a destination register)`t = [Rn]; [Rn] = min_unsigned(t, Ws); Wt = t`Atomic memory operations (LSE)
ldur	Wt, [Xn\|SP{, #imm9}]	10 111 0 00 01 0 imm9 00 Rn Rt0xB8400000 / mask 0xFFE00C00	Load of a word (32 bit) (unscaled, address: Rn + imm9)`Wt = [addr]; addr = Rn + imm9`Loads and stores
ldur	Xt, [Xn\|SP{, #imm9}]	11 111 0 00 01 0 imm9 00 Rn Rt0xF8400000 / mask 0xFFE00C00	Load of a double word (64 bit) (unscaled, address: Rn + imm9)`Xt = [addr]; addr = Rn + imm9`Loads and stores
ldurb	Wt, [Xn\|SP{, #imm9}]	00 111 0 00 01 0 imm9 00 Rn Rt0x38400000 / mask 0xFFE00C00	Load of a byte (zero-extended) (unscaled, address: Rn + imm9)`Wt = zext([addr]); addr = Rn + imm9`Loads and stores
ldurh	Wt, [Xn\|SP{, #imm9}]	01 111 0 00 01 0 imm9 00 Rn Rt0x78400000 / mask 0xFFE00C00	Load of a half word (zero-extended) (unscaled, address: Rn + imm9)`Wt = zext([addr]); addr = Rn + imm9`Loads and stores
ldursb	Xt, [Xn\|SP{, #imm9}]	00 111 0 00 10 0 imm9 00 Rn Rt0x38800000 / mask 0xFFE00C00	Load of a byte (sign-extended to 64 bit) (unscaled, address: Rn + imm9)`Xt = sext([addr]); addr = Rn + imm9`Loads and stores
ldursb	Wt, [Xn\|SP{, #imm9}]	00 111 0 00 11 0 imm9 00 Rn Rt0x38C00000 / mask 0xFFE00C00	Load of a byte (sign-extended to 32 bit) (unscaled, address: Rn + imm9)`Wt = sext([addr]); addr = Rn + imm9`Loads and stores
ldursh	Xt, [Xn\|SP{, #imm9}]	01 111 0 00 10 0 imm9 00 Rn Rt0x78800000 / mask 0xFFE00C00	Load of a half word (sign-extended to 64 bit) (unscaled, address: Rn + imm9)`Xt = sext([addr]); addr = Rn + imm9`Loads and stores
ldursh	Wt, [Xn\|SP{, #imm9}]	01 111 0 00 11 0 imm9 00 Rn Rt0x78C00000 / mask 0xFFE00C00	Load of a half word (sign-extended to 32 bit) (unscaled, address: Rn + imm9)`Wt = sext([addr]); addr = Rn + imm9`Loads and stores
ldursw	Xt, [Xn\|SP{, #imm9}]	10 111 0 00 10 0 imm9 00 Rn Rt0xB8800000 / mask 0xFFE00C00	Load of a word (sign-extended to 64 bit) (unscaled, address: Rn + imm9)`Xt = sext([addr]); addr = Rn + imm9`Loads and stores
ldxp	Rt, Rt2, [Xn\|SP]	1 sz 001000 0 1 1 11111 0 Rt2 Rn Rt0x887F0000 / mask 0xBFFF8000	Load of a register pair (exclusive)`Rt = [Rn]; Rt2 = [Rn + size]; set the exclusive monitor`Loads and stores
ldxr	Wt, [Xn\|SP]	10 001000 0 1 0 11111 0 11111 Rn Rt0x885F7C00 / mask 0xFFFFFC00	Load-exclusive: sets the exclusive monitor (word)`Rt = [Rn]; set the exclusive monitor`Loads and stores
ldxr	Xt, [Xn\|SP]	11 001000 0 1 0 11111 0 11111 Rn Rt0xC85F7C00 / mask 0xFFFFFC00	Load-exclusive: sets the exclusive monitor (double word)`Rt = [Rn]; set the exclusive monitor`Loads and stores
ldxrb	Wt, [Xn\|SP]	00 001000 0 1 0 11111 0 11111 Rn Rt0x085F7C00 / mask 0xFFFFFC00	Load-exclusive: sets the exclusive monitor (byte)`Rt = [Rn]; set the exclusive monitor`Loads and stores
ldxrh	Wt, [Xn\|SP]	01 001000 0 1 0 11111 0 11111 Rn Rt0x485F7C00 / mask 0xFFFFFC00	Load-exclusive: sets the exclusive monitor (half word)`Rt = [Rn]; set the exclusive monitor`Loads and stores
lslv	Rd, Rn, Rmalso shown as: lsl	sf 0 0 11010110 Rm 001000 Rn Rd0x1AC02000 / mask 0x7FE0FC00	Shift left by a register (amount modulo width)`Rd = Rn << (Rm mod width)`Shift and rotate
lsrv	Rd, Rn, Rmalso shown as: lsr	sf 0 0 11010110 Rm 001001 Rn Rd0x1AC02400 / mask 0x7FE0FC00	Shift right unsigned by a register`Rd = Rn >> (Rm mod width)`Shift and rotate
madd	Rd, Rn, Rm, Raalso shown as: mul	sf 00 11011 000 Rm 0 Ra Rn Rd0x1B000000 / mask 0x7FE08000	Multiply and add (Ra + Rn * Rm)`Rd = Ra + Rn * Rm`Arithmetic
mla	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 10010 1 Rn Rd0x0E209400 / mask 0xBF20FC00	Multiplication with addition to the destination`for every element: Vd[i] = Vd[i] + Vn[i] * Vm[i]`Vector (SIMD)
mla	Vd.T, Vn.T, Vm.Ts[index]	0 Q 1 01111 size L M Rm 0000 H 0 Rn Rd0x2F000000 / mask 0xBF00F400	Multiplication by an element, added to the destination`for every element: Vd[i] = Vd[i] + Vn[i] * Vm[index]`Vector (SIMD)
mls	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 10010 1 Rn Rd0x2E209400 / mask 0xBF20FC00	Multiplication with subtraction from the destination`for every element: Vd[i] = Vd[i] - Vn[i] * Vm[i]`Vector (SIMD)
mls	Vd.T, Vn.T, Vm.Ts[index]	0 Q 1 01111 size L M Rm 0100 H 0 Rn Rd0x2F004000 / mask 0xBF00F400	Multiplication by an element, subtracted from the destination`for every element: Vd[i] = Vd[i] - Vn[i] * Vm[index]`Vector (SIMD)
movi	Vd.T, #imm8{, lsl #amount}	0 Q 0 0111100000 abc 0 cm 0 01 defgh Rd0x0F000400 / mask 0xBFF89C00	Load of a 32-bit constant (one byte, shifted) into all elements`Vd = imm8 << (8 * cm) in every 32 bits`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 0 0111100000 abc 10 c 0 01 defgh Rd0x0F008400 / mask 0xBFF8DC00	Load of a 16-bit constant (one byte, shifted) into all elements`Vd = imm8 << (8 * c) in every 16 bits`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 0 0111100000 abc 110 c 01 defgh Rd0x0F00C400 / mask 0xBFF8EC00	Load of a 32-bit constant (one byte with ones shifted in) into all elements`Vd = (imm8 << 8 * (c+1)) \| ones`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 0 0111100000 abc 1110 01 defgh Rd0x0F00E400 / mask 0xBFF8FC00	Load of a byte into all elements`Vd = imm8 in every byte`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 1 0111100000 abc 1110 01 defgh Rd0x2F00E400 / mask 0xBFF8FC00	Load of a 64-bit constant, every bit of the byte stands for a byte`Vd = each bit of imm8 expanded to a byte`Vector (SIMD)
movk	Rd, #imm16{, lsl #shift}	sf 1 1 100101 hw imm16 Rd0x72800000 / mask 0x7F800000	Insertion of 16 bits of a constant into a register, the other bits stay`Rd[hw16 + 15 : hw16] = imm16`Constants and addresses
movn	Rd, #imm16{, lsl #shift}also shown as: mov	sf 0 0 100101 hw imm16 Rd0x12800000 / mask 0x7F800000	Load of an inverted constant into a register (16 bit, shifted by 0/16/32/48)`Rd = ~(imm16 << (hw * 16))`Constants and addresses
movz	Rd, #imm16{, lsl #shift}also shown as: mov	sf 1 0 100101 hw imm16 Rd0x52800000 / mask 0x7F800000	Load of a constant into a register (16 bit, shifted by 0/16/32/48, the rest 0)`Rd = imm16 << (hw * 16)`Constants and addresses
mrs	Xt, sysreg	1101010100 1 1 o0 op1 CRn CRm op2 Rt0xD5300000 / mask 0xFFF00000	Read of a system register`Xt = sysreg`System and privileged
msr	sysreg, Xt	1101010100 0 1 o0 op1 CRn CRm op2 Rt0xD5100000 / mask 0xFFF00000	Write of a system register`sysreg = Xt`System and privileged
msub	Rd, Rn, Rm, Raalso shown as: mneg	sf 00 11011 000 Rm 1 Ra Rn Rd0x1B008000 / mask 0x7FE08000	Multiply and subtract (Ra - Rn * Rm)`Rd = Ra - Rn * Rm`Arithmetic
mul	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 10011 1 Rn Rd0x0E209C00 / mask 0xBF20FC00	Multiplication of the elements (the low half of the result)`for every element: Vd[i] = Vn[i] * Vm[i]`Vector (SIMD)
mul	Vd.T, Vn.T, Vm.Ts[index]	0 Q 0 01111 size L M Rm 1000 H 0 Rn Rd0x0F008000 / mask 0xBF00F400	Multiplication by an element`for every element: Vd[i] = Vn[i] * Vm[index]`Vector (SIMD)
mvni	Vd.T, #imm8{, lsl #amount}	0 Q 1 0111100000 abc 0 cm 0 01 defgh Rd0x2F000400 / mask 0xBFF89C00	Load of the negation of a 32-bit constant into all elements`Vd = ~(imm8 << (8 * cm))`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 1 0111100000 abc 10 c 0 01 defgh Rd0x2F008400 / mask 0xBFF8DC00	Load of the negation of a 16-bit constant into all elements`Vd = ~(imm8 << (8 * c))`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 1 0111100000 abc 110 c 01 defgh Rd0x2F00C400 / mask 0xBFF8EC00	Load of the negation of a 32-bit constant (with ones shifted in)`Vd = ~((imm8 << 8 * (c+1)) \| ones)`Vector (SIMD)
neg	Vd.T, Vn.T	0 Q 1 01110 size 10000 01011 10 Rn Rd0x2E20B800 / mask 0xBF3FFC00	Negation`for every element: Vd[i] = -Vn[i]`Vector (SIMD)
not	Vd.T, Vn.Talso shown as: mvn	0 Q 1 01110 00 10000 00101 10 Rn Rd0x2E205800 / mask 0xBFFFFC00	Bitwise NOT`Vd = ~Vn`Vector (SIMD)
orn	Rd, Rn, Rm{, shift #imm6}also shown as: mvn	sf 0 1 01010 shift 1 Rm imm6 Rn Rd0x2A200000 / mask 0x7F200000	Bitwise OR with an inverted operand`Rd = Rn OR ~shift(Rm, imm6)`Logic and bits
orn	Vd.T, Vn.T, Vm.T	0 Q 0 01110 11 1 Rm 00011 1 Rn Rd0x0EE01C00 / mask 0xBFE0FC00	Bitwise OR with an inverted operand`Vd = Vn OR ~Vm`Vector (SIMD)
orr	Rd, Rn, #imm (bit pattern)also shown as: mov	sf 0 1 100100 N immr imms Rn Rd0x32000000 / mask 0x7F800000	Bitwise OR with a bit pattern as constant`Rd = Rn OR decode_bitmask(N, imms, immr) (Rd may be SP)`Logic and bits
	Rd, Rn, Rm{, shift #imm6}also shown as: mov	sf 0 1 01010 shift 0 Rm imm6 Rn Rd0x2A000000 / mask 0x7F200000	Bitwise OR (register, shifted); mov Rd, Rm is orr with xzr`Rd = Rn OR shift(Rm, imm6)`Logic and bits
	Vd.T, Vn.T, Vm.Talso shown as: mov	0 Q 0 01110 10 1 Rm 00011 1 Rn Rd0x0EA01C00 / mask 0xBFE0FC00	Bitwise OR (mov Vd, Vn is orr with Vn = Vm)`Vd = Vn OR Vm`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 0 0111100000 abc 0 cm 1 01 defgh Rd0x0F001400 / mask 0xBFF89C00	Bitwise OR with a 32-bit constant (one byte, shifted)`Vd = Vd \| (imm8 << (8 * cm))`Vector (SIMD)
	Vd.T, #imm8{, lsl #amount}	0 Q 0 0111100000 abc 10 c 1 01 defgh Rd0x0F009400 / mask 0xBFF8DC00	Bitwise OR with a 16-bit constant (one byte, shifted)`Vd = Vd \| (imm8 << (8 * c))`Vector (SIMD)
pacga	Xd, Xn, Xm\|SP	1 0 0 11010110 Rm 001100 Rn Rd0x9AC03000 / mask 0xFFE0FC00	Computation of a generic authentication code`Xd[63:32] = pac_code(Xn, Xm); Xd[31:0] = 0`Pointer authentication (PAC)
pacia	Xd, Xn\|SPalso shown as: pacib, pacda, pacdb, autia, autib, autda, autdb	1 1 0 11010110 00001 000 opc Rn Rd0xDAC10000 / mask 0xFFFFE000	Signing (pac...) or authenticating (aut...) of a pointer with a key (ia, ib for instructions, da, db for data) and a modifier (Xn)`Xd = pac(Xd, key, Xn) or Xd = aut(Xd, key, Xn)`Pointer authentication (PAC)
pmul	Vd.T, Vn.T, Vm.T	0 Q 1 01110 00 1 Rm 10011 1 Rn Rd0x2E209C00 / mask 0xBFE0FC00	Polynomial multiplication of the elements (byte, carry-less)`for every element: Vd[i] = Vn[i] * Vm[i] over GF(2)`Vector (SIMD)
pmull	Vd.Tb, Vn.Ta, Vm.Taalso shown as: pmull2	0 Q 0 01110 size 1 Rm 1110 00 Rn Rd0x0E20E000 / mask 0xBF20FC00	Polynomial multiplication with widening (carry-less; the 1Q form needs the crypto extension)`for every element: Vd[i] = Vn[i] * Vm[i] over GF(2)`Vector (SIMD)
prfm	prfop, [Xn\|SP{, #imm12}]	11 111 0 01 10 imm12 Rn Rt0xF9800000 / mask 0xFFC00000	Prefetch of a cache line (hint)`prefetch the cache line at addr (a hint)`Loads and stores
	prfop, [Xn\|SP, Rm{, extend {#amount}}]	11 111 0 00 10 1 Rm option S 10 Rn Rt0xF8A00800 / mask 0xFFE00C00	Prefetch of a cache line (hint) (register address)`prefetch the cache line at addr (a hint)`Loads and stores
	prfop, label	11 011 0 00 imm19 Rt0xD8000000 / mask 0xFF000000	Prefetch relative to the program counter (hint)`prefetch the cache line at pc + sext(imm19 << 2)`Loads and stores
prfum	prfop, [Xn\|SP{, #imm9}]	11 111 0 00 10 0 imm9 00 Rn Rt0xF8800000 / mask 0xFFE00C00	Prefetch of a cache line (hint) (unscaled)`prefetch the cache line at addr (a hint)`Loads and stores
raddhn	Vd.Tb, Vn.Ta, Vm.Taalso shown as: raddhn2	0 Q 1 01110 size 1 Rm 0100 00 Rn Rd0x2E204000 / mask 0xBF20FC00	Addition with narrowing (high half; raddhn with rounding) (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = high half of (Vn[i] + Vm[i])`Vector (SIMD)
rbit	Rd, Rn	sf 1 0 11010110 00000 000000 Rn Rd0x5AC00000 / mask 0x7FFFFC00	Reversal of the bit order`Rd = reverse_bits(Rn)`Logic and bits
rbit	Vd.T, Vn.T	0 Q 1 01110 01 10000 00101 10 Rn Rd0x2E605800 / mask 0xBFFFFC00	Reversal of the bit order in every byte`for every element: Vd[i] = reverse_bits(Vn[i])`Vector (SIMD)
ret	{Xn}	1101011 0 0 10 11111 000000 Rn 000000xD65F0000 / mask 0xFFFFFC1F	Return from the function (address in x30 if no register is given)`pc = Xn (default x30)`Branches and calls
rev	Wd, Wn	0 1 0 11010110 00000 000010 Rn Rd0x5AC00800 / mask 0xFFFFFC00	Reversal of the bytes of a 32-bit value (little/big endian)`Wd = reverse_bytes(Wn)`Logic and bits
rev	Xd, Xn	1 1 0 11010110 00000 000011 Rn Rd0xDAC00C00 / mask 0xFFFFFC00	Reversal of the bytes of a 64-bit value (little/big endian)`Xd = reverse_bytes(Xn)`Logic and bits
rev16	Rd, Rn	sf 1 0 11010110 00000 000001 Rn Rd0x5AC00400 / mask 0x7FFFFC00	Reversal of the bytes in each half word`Rd = reverse_bytes_in_each_16_bits(Rn)`Logic and bits
rev16	Vd.T, Vn.T	0 Q 0 01110 00 10000 00001 10 Rn Rd0x0E201800 / mask 0xBFFFFC00	Swap of the bytes in every 16-bit element`for every element: Vd[i] = reverse(Vn) per 16 bits`Vector (SIMD)
rev32	Xd, Xn	1 1 0 11010110 00000 000010 Rn Rd0xDAC00800 / mask 0xFFFFFC00	Reversal of the bytes in each 32-bit half of a 64-bit register`Xd = reverse_bytes_in_each_32_bits(Xn)`Logic and bits
rev32	Vd.T, Vn.T	0 Q 1 01110 size 10000 00000 10 Rn Rd0x2E200800 / mask 0xBF3FFC00	Reversal of the order of the elements in every 32-bit block`for every element: Vd[i] = reverse(Vn) per 32 bits`Vector (SIMD)
rev64	Vd.T, Vn.T	0 Q 0 01110 size 10000 00000 10 Rn Rd0x0E200800 / mask 0xBF3FFC00	Reversal of the order of the elements in every 64-bit block`for every element: Vd[i] = reverse(Vn) per 64 bits`Vector (SIMD)
rmif	Xn, #imm6, #nzcv	1 0 1 11010000 imm6 00001 Rn 0 nzcv0xBA000400 / mask 0xFFE07C10	Rotation of a register into the flags (masked)`flags = bits of (Xn rotated right by imm6) where the mask nzcv is set`Flags: N Z C VSystem and privileged
rorv	Rd, Rn, Rmalso shown as: ror	sf 0 0 11010110 Rm 001011 Rn Rd0x1AC02C00 / mask 0x7FE0FC00	Rotate right by a register`Rd = rotate_right(Rn, Rm mod width)`Shift and rotate
rshrn	Vd.Tb, Vn.Ta, #shiftalso shown as: rshrn2	0 Q 0 011110 0 immh immb 10001 1 Rn Rd0x0F008C00 / mask 0xBFC0FC00	Shift right with narrowing and rounding (Q = 1: name with 2)`for every element: Vd[i] = round(Vn[i] >> shift)`Vector (SIMD)
rsubhn	Vd.Tb, Vn.Ta, Vm.Taalso shown as: rsubhn2	0 Q 1 01110 size 1 Rm 0110 00 Rn Rd0x2E206000 / mask 0xBF20FC00	Subtraction with narrowing (high half; rsubhn with rounding) (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = high half of (Vn[i] - Vm[i])`Vector (SIMD)
saba	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 01111 1 Rn Rd0x0E207C00 / mask 0xBF20FC00	Addition of the absolute difference to the destination (signed)`for every element: Vd[i] = Vd[i] + abs(Vn[i] - Vm[i])`Vector (SIMD)
sabal	Vd.Tb, Vn.Ta, Vm.Taalso shown as: sabal2	0 Q 0 01110 size 1 Rm 0101 00 Rn Rd0x0E205000 / mask 0xBF20FC00	Addition of the absolute difference with widening (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vd[i] + abs(Vn[i] - Vm[i])`Vector (SIMD)
sabd	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 01110 1 Rn Rd0x0E207400 / mask 0xBF20FC00	Absolute difference (signed)`for every element: Vd[i] = abs(Vn[i] - Vm[i])`Vector (SIMD)
sabdl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: sabdl2	0 Q 0 01110 size 1 Rm 0111 00 Rn Rd0x0E207000 / mask 0xBF20FC00	Absolute difference with widening (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = abs(Vn[i] - Vm[i]) (wide result)`Vector (SIMD)
sadalp	Vd.T, Vn.T	0 Q 0 01110 size 10000 00110 10 Rn Rd0x0E206800 / mask 0xBF3FFC00	Pairwise addition with widening, added to the destination (signed)`for every element: Vd[i] = Vd[i] + Vn[2i] + Vn[2i+1]`Vector (SIMD)
saddl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: saddl2	0 Q 0 01110 size 1 Rm 0000 00 Rn Rd0x0E200000 / mask 0xBF20FC00	Addition with widening (both operands become twice as wide) (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] + Vm[i] (wide result)`Vector (SIMD)
saddlp	Vd.T, Vn.T	0 Q 0 01110 size 10000 00010 10 Rn Rd0x0E202800 / mask 0xBF3FFC00	Pairwise addition of adjacent elements with widening (signed)`for every element: Vd[i] = Vn[2i] + Vn[2i+1]`Vector (SIMD)
saddlv	Vd, Vn.T	0 Q 0 01110 size 11000 00011 10 Rn Rd0x0E303800 / mask 0xBF3FFC00	Sum of all elements with widening (signed)`Vd = sum of all elements of Vn`Vector (SIMD)
saddw	Vd.Tb, Vn.Ta, Vm.Taalso shown as: saddw2	0 Q 0 01110 size 1 Rm 0001 00 Rn Rd0x0E201000 / mask 0xBF20FC00	Addition of a wide and a narrow operand (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] + Vm[i] (Vn is wide)`Vector (SIMD)
sbc	Rd, Rn, Rmalso shown as: ngc	sf 1 0 11010000 Rm 000000 Rn Rd0x5A000000 / mask 0x7FE0FC00	Subtraction with borrow (C)`Rd = Rn - Rm - (1 - C)`Arithmetic
sbcs	Rd, Rn, Rmalso shown as: ngcs	sf 1 1 11010000 Rm 000000 Rn Rd0x7A000000 / mask 0x7FE0FC00	Subtraction with borrow, sets the flags`Rd = Rn - Rm - (1 - C)`Flags: N Z C VArithmetic
sbfm	Rd, Rn, #immr, #immsalso shown as: asr, sbfiz, sbfx, sxtb, sxth, sxtw	sf 0 0 100110 N immr imms Rn Rd0x13000000 / mask 0x7F800000	Bitfield move with sign extension (base form of asr, sbfx, sxtb ...)`Rd = sign-extended field of Rn selected by immr, imms`Bitfields
scvtf	Fd, Rn	sf 0 0 11110 ftype 1 00 010 000000 Rn Rd0x1E220000 / mask 0x7F3FFC00	Conversion of a signed integer to floating point`Fd = (float) sext(Rn)`Floating point (scalar)
scvtf	Vd.T, Vn.T	0 Q 0 01110 0 sz 10000 11101 10 Rn Rd0x0E21D800 / mask 0xBFBFFC00	Conversion of a signed integer to floating point`for every element: Vd[i] = (float) Vn[i]`Vector (SIMD)
sdiv	Rd, Rn, Rm	sf 0 0 11010110 Rm 000011 Rn Rd0x1AC00C00 / mask 0x7FE0FC00	Signed division (division by 0 gives 0)`Rd = Rn / Rm`Arithmetic
sdot	Vd.4S, Vn.16B, Vm.16B	0 Q 0 01110 10 0 Rm 10010 1 Rn Rd0x0E809400 / mask 0xBFE0FC00	Dot product of four bytes each (signed), added to the 32-bit destination`for every element: Vd[i] = Vd[i] + sum of Vn[4i+k] * Vm[4i+k]`Vector (SIMD)
sete	[Xd]!, Xn!, Xsalso shown as: seten, setet, setetn	00 011 0 01 11 0 Rs 10 o 01 Rn Rd0x19C08400 / mask 0xFFE0CC00	Fill of a memory block with a byte, epilogue (the three instructions p, m, e are executed in sequence)`fill Xn bytes at [Xd] with Xs[7:0]; Xd and Xn are updated`Memory copy and set
setge	[Xd]!, Xn!, Xsalso shown as: setgen, setget, setgetn	00 011 1 01 11 0 Rs 10 o 01 Rn Rd0x1DC08400 / mask 0xFFE0CC00	Fill of a memory block with a byte with tags, epilogue (the three instructions p, m, e are executed in sequence)`fill Xn bytes at [Xd] with Xs[7:0]; Xd and Xn are updated`Memory copy and set
setgm	[Xd]!, Xn!, Xsalso shown as: setgmn, setgmt, setgmtn	00 011 1 01 11 0 Rs 01 o 01 Rn Rd0x1DC04400 / mask 0xFFE0CC00	Fill of a memory block with a byte with tags, main part (the three instructions p, m, e are executed in sequence)`fill Xn bytes at [Xd] with Xs[7:0]; Xd and Xn are updated`Memory copy and set
setgp	[Xd]!, Xn!, Xsalso shown as: setgpn, setgpt, setgptn	00 011 1 01 11 0 Rs 00 o 01 Rn Rd0x1DC00400 / mask 0xFFE0CC00	Fill of a memory block with a byte with tags, prologue (the three instructions p, m, e are executed in sequence)`fill Xn bytes at [Xd] with Xs[7:0]; Xd and Xn are updated`Memory copy and set
setm	[Xd]!, Xn!, Xsalso shown as: setmn, setmt, setmtn	00 011 0 01 11 0 Rs 01 o 01 Rn Rd0x19C04400 / mask 0xFFE0CC00	Fill of a memory block with a byte, main part (the three instructions p, m, e are executed in sequence)`fill Xn bytes at [Xd] with Xs[7:0]; Xd and Xn are updated`Memory copy and set
setp	[Xd]!, Xn!, Xsalso shown as: setpn, setpt, setptn	00 011 0 01 11 0 Rs 00 o 01 Rn Rd0x19C00400 / mask 0xFFE0CC00	Fill of a memory block with a byte, prologue (the three instructions p, m, e are executed in sequence)`fill Xn bytes at [Xd] with Xs[7:0]; Xd and Xn are updated`Memory copy and set
sha1c	Qd, Sn, Vm.4Salso shown as: sha1p, sha1m, sha1su0, sha256h, sha256h2, sha256su1	01011110 00 0 Rm 0 opc 00 Rn Rd0x5E000000 / mask 0xFFE08C00	SHA-1 and SHA-256 hash update (sha1c: choose, sha1p: parity, sha1m: majority, sha256h, sha256h2: hash update, ...su: message schedule)`Vd = hash_update(Vd, Vn, Vm)`Cryptography
sha1h	Sd, Snalso shown as: sha1su1, sha256su0	01011110 00 10100 000 opc 10 Rn Rd0x5E280800 / mask 0xFFFFCC00	SHA-1 rotation (sha1h) and message schedule (sha1su1, sha256su0)`Sd = rotate_left(Sn, 30)`Cryptography
sha512h	Qd, Qn, Vm.2Dalso shown as: sha512h2, sha512su1, rax1	11001110 011 Rm 1 000 opc Rn Rd0xCE608000 / mask 0xFFE0F000	SHA-512 hash update (sha512h, sha512h2), message schedule (sha512su1) and rotation (rax1: rotate and exclusive OR, also for SHA-3)`Vd = hash_update(Vd, Vn, Vm)`Cryptography
sha512su0	Vd.2D, Vn.2Dalso shown as: sm4e	11001110 110 00000 1000 0 x Rn Rd0xCEC08000 / mask 0xFFFFF800	SHA-512 message schedule (sha512su0) and SM4 encryption of four rounds (sm4e)`Vd = message_schedule(Vd, Vn)`Cryptography
shadd	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 00000 1 Rn Rd0x0E200400 / mask 0xBF20FC00	Halving addition (signed)`for every element: Vd[i] = (Vn[i] + Vm[i]) >> 1`Vector (SIMD)
shl	Vd.T, Vn.T, #shift	0 Q 0 011110 immh immb 01010 1 Rn Rd0x0F005400 / mask 0xBF80FC00	Shift left`for every element: Vd[i] = Vn[i] << shift`Vector (SIMD)
shll	Vd.Ta, Vn.Tb, #shiftalso shown as: shll2	0 Q 1 01110 size 10000 10011 10 Rn Rd0x2E213800 / mask 0xBF3FFC00	Widening with a left shift by the element size`for every element: Vd[i] = Vn[i] << esize`Vector (SIMD)
shrn	Vd.Tb, Vn.Ta, #shiftalso shown as: shrn2	0 Q 0 011110 0 immh immb 10000 1 Rn Rd0x0F008400 / mask 0xBFC0FC00	Shift right with narrowing (Q = 1: name with 2)`for every element: Vd[i] = Vn[i] >> shift`Vector (SIMD)
shsub	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 00100 1 Rn Rd0x0E202400 / mask 0xBF20FC00	Halving subtraction (signed)`for every element: Vd[i] = (Vn[i] - Vm[i]) >> 1`Vector (SIMD)
sli	Vd.T, Vn.T, #shift	0 Q 1 011110 immh immb 01010 1 Rn Rd0x2F005400 / mask 0xBF80FC00	Shift left and insert (the low bits of the destination stay)`for every element: Vd[i] = (Vd[i] & low_mask) \| (Vn[i] << shift)`Vector (SIMD)
sm3partw1	Vd.4S, Vn.4S, Vm.4Salso shown as: sm3partw2, sm4ekey	11001110 011 Rm 1100 opc Rn Rd0xCE60C000 / mask 0xFFE0F000	SM3 message expansion (sm3partw1, sm3partw2) and SM4 key schedule (sm4ekey)`Vd = expand(Vn, Vm)`Cryptography
sm3ss1	Vd.4S, Vn.4S, Vm.4S, Va.4S	11001110 010 Rm 0 Ra Rn Rd0xCE400000 / mask 0xFFE08000	SM3 helper value`Vd = SM3SS1(Vn, Vm, Va)`Cryptography
sm3tt1a	Vd.4S, Vn.4S, Vm.S[imm2]also shown as: sm3tt1b, sm3tt2a, sm3tt2b	11001110 010 Rm 10 imm2 opc Rn Rd0xCE408000 / mask 0xFFE0C000	SM3 compression function (four variants)`Vd = SM3TT(Vd, Vn, Vm[imm2])`Cryptography
smaddl	Xd, Wn, Wm, Xaalso shown as: smull	1 00 11011 001 Rm 0 Ra Rn Rd0x9B200000 / mask 0xFFE08000	Signed multiply 32 x 32 bit, added to 64 bit`Xd = Xa + sext(Wn) * sext(Wm)`Arithmetic
smax	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 01100 1 Rn Rd0x0E206400 / mask 0xBF20FC00	Maximum of the elements (signed)`for every element: Vd[i] = max_signed(Vn[i], Vm[i])`Vector (SIMD)
smaxp	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 10100 1 Rn Rd0x0E20A400 / mask 0xBF20FC00	Maximum of adjacent element pairs (signed)`for every element: Vd[i] = max_signed of each pair of (Vn:Vm)`Vector (SIMD)
smaxv	Vd, Vn.T	0 Q 0 01110 size 11000 01010 10 Rn Rd0x0E30A800 / mask 0xBF3FFC00	Maximum of all elements (signed)`Vd = max_signed of all elements of Vn`Vector (SIMD)
smc	#imm16	11010100 000 imm16 000 110xD4000003 / mask 0xFFE0001F	Secure monitor call (exception level 3)`raise a secure monitor call exception`System and privileged
smin	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 01101 1 Rn Rd0x0E206C00 / mask 0xBF20FC00	Minimum of the elements (signed)`for every element: Vd[i] = min_signed(Vn[i], Vm[i])`Vector (SIMD)
sminp	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 10101 1 Rn Rd0x0E20AC00 / mask 0xBF20FC00	Minimum of adjacent element pairs (signed)`for every element: Vd[i] = min_signed of each pair of (Vn:Vm)`Vector (SIMD)
sminv	Vd, Vn.T	0 Q 0 01110 size 11000 11010 10 Rn Rd0x0E31A800 / mask 0xBF3FFC00	Minimum of all elements (signed)`Vd = min_signed of all elements of Vn`Vector (SIMD)
smlal	Vd.Tb, Vn.Ta, Vm.Taalso shown as: smlal2	0 Q 0 01110 size 1 Rm 1000 00 Rn Rd0x0E208000 / mask 0xBF20FC00	Multiplication with widening, added to the destination (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vd[i] + Vn[i] * Vm[i]`Vector (SIMD)
smlal	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: smlal2	0 Q 0 01111 size L M Rm 0010 H 0 Rn Rd0x0F002000 / mask 0xBF00F400	Multiplication by an element with widening, added to the destination (signed) (Q = 1: name with 2)`for every element: Vd[i] = Vd[i] + Vn[i] * Vm[index]`Vector (SIMD)
smlsl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: smlsl2	0 Q 0 01110 size 1 Rm 1010 00 Rn Rd0x0E20A000 / mask 0xBF20FC00	Multiplication with widening, subtracted from the destination (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vd[i] - Vn[i] * Vm[i]`Vector (SIMD)
smlsl	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: smlsl2	0 Q 0 01111 size L M Rm 0110 H 0 Rn Rd0x0F006000 / mask 0xBF00F400	Multiplication by an element with widening, subtracted from the destination (signed) (Q = 1: name with 2)`for every element: Vd[i] = Vd[i] - Vn[i] * Vm[index]`Vector (SIMD)
smmla	Vd.4S, Vn.16B, Vm.16B	0 1 0 01110 10 0 Rm 10100 1 Rn Rd0x4E80A400 / mask 0xFFE0FC00	Matrix multiplication 2x8 times 8x2 (signed), added to the destination`Vd(2x2) = Vd(2x2) + Vn(2x8) * Vm(8x2)`Vector (SIMD)
smov	Rd, Vn.Ts[index]	0 Q 0 01110000 imm5 0 0101 1 Rn Rd0x0E002C00 / mask 0xBFE0FC00	Copy of an element into an integer register (signed)`Rd = sext(Vn[index])`Vector (SIMD)
smsubl	Xd, Wn, Wm, Xaalso shown as: smnegl	1 00 11011 001 Rm 1 Ra Rn Rd0x9B208000 / mask 0xFFE08000	Signed multiply 32 x 32 bit, subtracted from 64 bit`Xd = Xa - sext(Wn) * sext(Wm)`Arithmetic
smulh	Xd, Xn, Xm	1 00 11011 010 Rm 0 11111 Rn Rd0x9B407C00 / mask 0xFFE0FC00	Signed multiply, the high 64 bits of the result`Xd = (sext(Xn) * sext(Xm)) >> 64`Arithmetic
smull	Vd.Tb, Vn.Ta, Vm.Taalso shown as: smull2	0 Q 0 01110 size 1 Rm 1100 00 Rn Rd0x0E20C000 / mask 0xBF20FC00	Multiplication with widening (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] * Vm[i] (wide result)`Vector (SIMD)
smull	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: smull2	0 Q 0 01111 size L M Rm 1010 H 0 Rn Rd0x0F00A000 / mask 0xBF00F400	Multiplication by an element with widening (signed) (Q = 1: name with 2)`for every element: Vd[i] = Vn[i] * Vm[index]`Vector (SIMD)
sqabs	Vd.T, Vn.T	0 Q 0 01110 size 10000 00111 10 Rn Rd0x0E207800 / mask 0xBF3FFC00	Absolute value with saturation`for every element: Vd[i] = saturate(abs(Vn[i]))`Vector (SIMD)
sqadd	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 00001 1 Rn Rd0x0E200C00 / mask 0xBF20FC00	Addition with saturation (signed)`for every element: Vd[i] = saturate_signed(Vn[i] + Vm[i])`Vector (SIMD)
sqdmlal	Vd.Tb, Vn.Ta, Vm.Taalso shown as: sqdmlal2	0 Q 0 01110 size 1 Rm 1001 00 Rn Rd0x0E209000 / mask 0xBF20FC00	Doubling multiplication with widening and saturation, added to the destination`for every element: Vd[i] = saturate(Vd[i] + 2 * Vn[i] * Vm[i])`Vector (SIMD)
sqdmlal	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: sqdmlal2	0 Q 0 01111 size L M Rm 0011 H 0 Rn Rd0x0F003000 / mask 0xBF00F400	Doubling multiplication by an element with widening and saturation, added to the destination (Q = 1: name with 2)`for every element: Vd[i] = saturate(Vd[i] + 2 * Vn[i] * Vm[index])`Vector (SIMD)
sqdmlsl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: sqdmlsl2	0 Q 0 01110 size 1 Rm 1011 00 Rn Rd0x0E20B000 / mask 0xBF20FC00	Doubling multiplication with widening and saturation, subtracted from the destination`for every element: Vd[i] = saturate(Vd[i] - 2 * Vn[i] * Vm[i])`Vector (SIMD)
sqdmlsl	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: sqdmlsl2	0 Q 0 01111 size L M Rm 0111 H 0 Rn Rd0x0F007000 / mask 0xBF00F400	Doubling multiplication by an element with widening and saturation, subtracted from the destination (Q = 1: name with 2)`for every element: Vd[i] = saturate(Vd[i] - 2 * Vn[i] * Vm[index])`Vector (SIMD)
sqdmulh	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 10110 1 Rn Rd0x0E20B400 / mask 0xBF20FC00	Doubling multiplication, high half, with saturation`for every element: Vd[i] = saturate((2 * Vn[i] * Vm[i]) >> esize)`Vector (SIMD)
sqdmulh	Vd.T, Vn.T, Vm.Ts[index]	0 Q 0 01111 size L M Rm 1100 H 0 Rn Rd0x0F00C000 / mask 0xBF00F400	Doubling multiplication by an element, high half, with saturation`for every element: Vd[i] = saturate((2 * Vn[i] * Vm[index]) >> esize)`Vector (SIMD)
sqdmull	Vd.Tb, Vn.Ta, Vm.Taalso shown as: sqdmull2	0 Q 0 01110 size 1 Rm 1101 00 Rn Rd0x0E20D000 / mask 0xBF20FC00	Doubling multiplication with widening and saturation`for every element: Vd[i] = saturate(2 * Vn[i] * Vm[i])`Vector (SIMD)
sqdmull	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: sqdmull2	0 Q 0 01111 size L M Rm 1011 H 0 Rn Rd0x0F00B000 / mask 0xBF00F400	Doubling multiplication by an element with widening and saturation (Q = 1: name with 2)`for every element: Vd[i] = saturate(2 * Vn[i] * Vm[index])`Vector (SIMD)
sqneg	Vd.T, Vn.T	0 Q 1 01110 size 10000 00111 10 Rn Rd0x2E207800 / mask 0xBF3FFC00	Negation with saturation`for every element: Vd[i] = saturate(-Vn[i])`Vector (SIMD)
sqrdmlah	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 0 Rm 10000 1 Rn Rd0x2E008400 / mask 0xBF20FC00	Doubling multiplication, high half, with rounding and saturation, added to the destination`for every element: Vd[i] = saturate(Vd[i] + round((2 * Vn[i] * Vm[i]) >> esize))`Vector (SIMD)
sqrdmlsh	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 0 Rm 10001 1 Rn Rd0x2E008C00 / mask 0xBF20FC00	Doubling multiplication, high half, with rounding and saturation, subtracted from the destination`for every element: Vd[i] = saturate(Vd[i] - round((2 * Vn[i] * Vm[i]) >> esize))`Vector (SIMD)
sqrdmulh	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 10110 1 Rn Rd0x2E20B400 / mask 0xBF20FC00	Doubling multiplication, high half, with rounding and saturation`for every element: Vd[i] = saturate(round((2 * Vn[i] * Vm[i]) >> esize))`Vector (SIMD)
sqrdmulh	Vd.T, Vn.T, Vm.Ts[index]	0 Q 0 01111 size L M Rm 1101 H 0 Rn Rd0x0F00D000 / mask 0xBF00F400	Doubling multiplication by an element, high half, with rounding and saturation`for every element: Vd[i] = saturate(round((2 * Vn[i] * Vm[index]) >> esize))`Vector (SIMD)
sqrshl	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 01011 1 Rn Rd0x0E205C00 / mask 0xBF20FC00	Shift per element with rounding and saturation (signed)`for every element: Vd[i] = saturate_signed(round(Vn[i] << Vm[i]))`Vector (SIMD)
sqrshrn	Vd.Tb, Vn.Ta, #shiftalso shown as: sqrshrn2	0 Q 0 011110 0 immh immb 10011 1 Rn Rd0x0F009C00 / mask 0xBFC0FC00	Shift right with narrowing, rounding and saturation (signed) (Q = 1: name with 2)`for every element: Vd[i] = saturate_signed(round(Vn[i] >> shift))`Vector (SIMD)
sqrshrun	Vd.Tb, Vn.Ta, #shiftalso shown as: sqrshrun2	0 Q 1 011110 0 immh immb 10001 1 Rn Rd0x2F008C00 / mask 0xBFC0FC00	Shift right with narrowing, rounding and saturation (signed source, unsigned result) (Q = 1: name with 2)`for every element: Vd[i] = saturate_unsigned(round(Vn[i] >> shift))`Vector (SIMD)
sqshl	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 01001 1 Rn Rd0x0E204C00 / mask 0xBF20FC00	Shift per element with saturation (signed)`for every element: Vd[i] = saturate_signed(Vn[i] << Vm[i])`Vector (SIMD)
sqshl	Vd.T, Vn.T, #shift	0 Q 0 011110 immh immb 01110 1 Rn Rd0x0F007400 / mask 0xBF80FC00	Shift left with saturation (signed)`for every element: Vd[i] = saturate_signed(Vn[i] << shift)`Vector (SIMD)
sqshlu	Vd.T, Vn.T, #shift	0 Q 1 011110 immh immb 01100 1 Rn Rd0x2F006400 / mask 0xBF80FC00	Shift left with saturation (signed source, unsigned result)`for every element: Vd[i] = saturate_unsigned(Vn[i] << shift)`Vector (SIMD)
sqshrn	Vd.Tb, Vn.Ta, #shiftalso shown as: sqshrn2	0 Q 0 011110 0 immh immb 10010 1 Rn Rd0x0F009400 / mask 0xBFC0FC00	Shift right with narrowing and saturation (signed) (Q = 1: name with 2)`for every element: Vd[i] = saturate_signed(Vn[i] >> shift)`Vector (SIMD)
sqshrun	Vd.Tb, Vn.Ta, #shiftalso shown as: sqshrun2	0 Q 1 011110 0 immh immb 10000 1 Rn Rd0x2F008400 / mask 0xBFC0FC00	Shift right with narrowing and saturation (signed source, unsigned result) (Q = 1: name with 2)`for every element: Vd[i] = saturate_unsigned(Vn[i] >> shift)`Vector (SIMD)
sqsub	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 00101 1 Rn Rd0x0E202C00 / mask 0xBF20FC00	Subtraction with saturation (signed)`for every element: Vd[i] = saturate_signed(Vn[i] - Vm[i])`Vector (SIMD)
sqxtn	Vd.T, Vn.Talso shown as: sqxtn2	0 Q 0 01110 size 10000 10100 10 Rn Rd0x0E214800 / mask 0xBF3FFC00	Narrowing with saturation (signed)`for every element: Vd[i] = saturate_signed(Vn[i])`Vector (SIMD)
sqxtun	Vd.T, Vn.Talso shown as: sqxtun2	0 Q 1 01110 size 10000 10010 10 Rn Rd0x2E212800 / mask 0xBF3FFC00	Narrowing with saturation (signed source, unsigned result)`for every element: Vd[i] = saturate_unsigned(Vn[i])`Vector (SIMD)
srhadd	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 00010 1 Rn Rd0x0E201400 / mask 0xBF20FC00	Halving addition with rounding (signed)`for every element: Vd[i] = (Vn[i] + Vm[i] + 1) >> 1`Vector (SIMD)
sri	Vd.T, Vn.T, #shift	0 Q 1 011110 immh immb 01000 1 Rn Rd0x2F004400 / mask 0xBF80FC00	Shift right and insert (the high bits of the destination stay)`for every element: Vd[i] = (Vd[i] & high_mask) \| (Vn[i] >> shift)`Vector (SIMD)
srshl	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 01010 1 Rn Rd0x0E205400 / mask 0xBF20FC00	Shift per element with rounding (signed)`for every element: Vd[i] = round(Vn[i] << Vm[i])`Vector (SIMD)
srshr	Vd.T, Vn.T, #shift	0 Q 0 011110 immh immb 00100 1 Rn Rd0x0F002400 / mask 0xBF80FC00	Shift right with rounding (signed)`for every element: Vd[i] = round(Vn[i] >> shift)`Vector (SIMD)
srsra	Vd.T, Vn.T, #shift	0 Q 0 011110 immh immb 00110 1 Rn Rd0x0F003400 / mask 0xBF80FC00	Shift right with rounding and addition to the destination (signed)`for every element: Vd[i] = Vd[i] + round(Vn[i] >> shift)`Vector (SIMD)
sshl	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 1 Rm 01000 1 Rn Rd0x0E204400 / mask 0xBF20FC00	Shift left or right per element (signed)`for every element: Vd[i] = Vn[i] << Vm[i] (a negative count shifts right)`Vector (SIMD)
sshll	Vd.Ta, Vn.Tb, #shiftalso shown as: sshll2, sxtl, sxtl2	0 Q 0 011110 0 immh immb 10100 1 Rn Rd0x0F00A400 / mask 0xBFC0FC00	Widening with a left shift (signed; sxtl is a shift by 0)`for every element: Vd[i] = sext(Vn[i]) << shift`Vector (SIMD)
sshr	Vd.T, Vn.T, #shift	0 Q 0 011110 immh immb 00000 1 Rn Rd0x0F000400 / mask 0xBF80FC00	Shift right, signed (arithmetic) (signed)`for every element: Vd[i] = Vn[i] >> shift`Vector (SIMD)
ssra	Vd.T, Vn.T, #shift	0 Q 0 011110 immh immb 00010 1 Rn Rd0x0F001400 / mask 0xBF80FC00	Shift right and addition to the destination (signed)`for every element: Vd[i] = Vd[i] + (Vn[i] >> shift)`Vector (SIMD)
ssubl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: ssubl2	0 Q 0 01110 size 1 Rm 0010 00 Rn Rd0x0E202000 / mask 0xBF20FC00	Subtraction with widening (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] - Vm[i] (wide result)`Vector (SIMD)
ssubw	Vd.Tb, Vn.Ta, Vm.Taalso shown as: ssubw2	0 Q 0 01110 size 1 Rm 0011 00 Rn Rd0x0E203000 / mask 0xBF20FC00	Subtraction of a narrow operand from a wide one (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] - Vm[i] (Vn is wide)`Vector (SIMD)
st1	{Vt.T}, [Xn\|SP]	0 Q 0011000 0 000000 0111 size Rn Rt0x0C007000 / mask 0xBFFFF000	Store of one vector register to memory`[Rn] = Vt`Vector (SIMD)
	{Vt.T, Vt2.T}, [Xn\|SP]	0 Q 0011000 0 000000 1010 size Rn Rt0x0C00A000 / mask 0xBFFFF000	Store of 2 registers to memory`[Rn] = registers (2 registers)`Vector (SIMD)
	{Vt.T, Vt2.T, Vt3.T}, [Xn\|SP]	0 Q 0011000 0 000000 0110 size Rn Rt0x0C006000 / mask 0xBFFFF000	Store of 3 registers to memory`[Rn] = registers (3 registers)`Vector (SIMD)
	{Vt.T, Vt2.T, Vt3.T, Vt4.T}, [Xn\|SP]	0 Q 0011000 0 000000 0010 size Rn Rt0x0C002000 / mask 0xBFFFF000	Store of 4 registers to memory`[Rn] = registers (4 registers)`Vector (SIMD)
	{Vt.Ts}[index], [Xn\|SP]	0 Q 0011010 0 0 00000 e 0 S size Rn Rt0x0D000000 / mask 0xBFFF2000	Store of one element (lane) (one register)`[Rn] = Vt[index]`Vector (SIMD)
st2	{Vt.T, Vt2.T}, [Xn\|SP]	0 Q 0011000 0 000000 1000 size Rn Rt0x0C008000 / mask 0xBFFFF000	Store of 2 registers (elements interleaved) to memory`[Rn] = registers (2 registers (elements interleaved))`Vector (SIMD)
	{Vt.T, Vt2.T}, [Xn\|SP], Xm\|#imm	0 Q 0011001 0 0 Rm 1000 size Rn Rt0x0C808000 / mask 0xBFE0F000	Store of 2 registers (elements interleaved) with post-indexing`[Rn] = registers; Rn = Rn + Xm or the size`Vector (SIMD)
	{Vt.Ts, Vt2.Ts}[index], [Xn\|SP]	0 Q 0011010 0 1 00000 e 0 S size Rn Rt0x0D200000 / mask 0xBFFF2000	Store of one element (lane) of 2 registers`[Rn] = Vt[index]`Vector (SIMD)
st2g	Xt\|SP, [Xn\|SP], #imm9	11011001 101 imm9 01 Rn Rt0xD9A00400 / mask 0xFFE00C00	Store of the tag for 32 bytes (post-indexed)`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
	Xt\|SP, [Xn\|SP{, #imm9}]	11011001 101 imm9 10 Rn Rt0xD9A00800 / mask 0xFFE00C00	Store of the tag for 32 bytes`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
	Xt\|SP, [Xn\|SP, #imm9]!	11011001 101 imm9 11 Rn Rt0xD9A00C00 / mask 0xFFE00C00	Store of the tag for 32 bytes (pre-indexed)`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
st3	{Vt.T, Vt2.T, Vt3.T}, [Xn\|SP]	0 Q 0011000 0 000000 0100 size Rn Rt0x0C004000 / mask 0xBFFFF000	Store of 3 registers (elements interleaved) to memory`[Rn] = registers (3 registers (elements interleaved))`Vector (SIMD)
	{Vt.T, Vt2.T, Vt3.T}, [Xn\|SP], Xm\|#imm	0 Q 0011001 0 0 Rm 0100 size Rn Rt0x0C804000 / mask 0xBFE0F000	Store of 3 registers (elements interleaved) with post-indexing`[Rn] = registers; Rn = Rn + Xm or the size`Vector (SIMD)
	{Vt.Ts, Vt2.Ts, Vt3.Ts}[index], [Xn\|SP]	0 Q 0011010 0 0 00000 e 1 S size Rn Rt0x0D002000 / mask 0xBFFF2000	Store of one element (lane) of 3 registers`[Rn] = Vt[index]`Vector (SIMD)
st4	{Vt.T, Vt2.T, Vt3.T, Vt4.T}, [Xn\|SP]	0 Q 0011000 0 000000 0000 size Rn Rt0x0C000000 / mask 0xBFFFF000	Store of 4 registers (elements interleaved) to memory`[Rn] = registers (4 registers (elements interleaved))`Vector (SIMD)
	{Vt.T, Vt2.T, Vt3.T, Vt4.T}, [Xn\|SP], Xm\|#imm	0 Q 0011001 0 0 Rm 0000 size Rn Rt0x0C800000 / mask 0xBFE0F000	Store of 4 registers (elements interleaved) with post-indexing`[Rn] = registers; Rn = Rn + Xm or the size`Vector (SIMD)
	{Vt.Ts, Vt2.Ts, Vt3.Ts, Vt4.Ts}[index], [Xn\|SP]	0 Q 0011010 0 1 00000 e 1 S size Rn Rt0x0D202000 / mask 0xBFFF2000	Store of one element (lane) of 4 registers`[Rn] = Vt[index]`Vector (SIMD)
stg	Xt\|SP, [Xn\|SP], #imm9	11011001 001 imm9 01 Rn Rt0xD9200400 / mask 0xFFE00C00	Store of the tag of an address for 16 bytes (post-indexed)`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
	Xt\|SP, [Xn\|SP{, #imm9}]	11011001 001 imm9 10 Rn Rt0xD9200800 / mask 0xFFE00C00	Store of the tag of an address for 16 bytes`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
	Xt\|SP, [Xn\|SP, #imm9]!	11011001 001 imm9 11 Rn Rt0xD9200C00 / mask 0xFFE00C00	Store of the tag of an address for 16 bytes (pre-indexed)`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
stgp	Xt, Xt2, [Xn\|SP], #imm7	01 101 0 001 0 imm7 Rt2 Rn Rt0x68800000 / mask 0xFFC00000	Store of a register pair and the tag (post-indexed)`[addr] = Xt, Xt2; tag of [addr] = tag of Rn`Memory tagging (MTE)
	Xt, Xt2, [Xn\|SP{, #imm7}]	01 101 0 010 0 imm7 Rt2 Rn Rt0x69000000 / mask 0xFFC00000	Store of a register pair and the tag`[addr] = Xt, Xt2; tag of [addr] = tag of Rn`Memory tagging (MTE)
	Xt, Xt2, [Xn\|SP, #imm7]!	01 101 0 011 0 imm7 Rt2 Rn Rt0x69800000 / mask 0xFFC00000	Store of a register pair and the tag (pre-indexed)`[addr] = Xt, Xt2; tag of [addr] = tag of Rn`Memory tagging (MTE)
stllr	Wt, [Xn\|SP]also shown as: stllrb, stllrh	size 001000 1 0 0 11111 0 11111 Rn Rt0x089F7C00 / mask 0x3FFFFC00	Store with release for an ordered memory region (LORegion; b = byte, h = half word)`[Rn] = Wt`Loads and stores
stlr	Wt, [Xn\|SP]	10 001000 1 0 0 11111 1 11111 Rn Rt0x889FFC00 / mask 0xFFFFFC00	Store with release (word)`release; [Rn] = Rt`Loads and stores
stlr	Xt, [Xn\|SP]	11 001000 1 0 0 11111 1 11111 Rn Rt0xC89FFC00 / mask 0xFFFFFC00	Store with release (double word)`release; [Rn] = Rt`Loads and stores
stlrb	Wt, [Xn\|SP]	00 001000 1 0 0 11111 1 11111 Rn Rt0x089FFC00 / mask 0xFFFFFC00	Store with release (byte)`release; [Rn] = Rt`Loads and stores
stlrh	Wt, [Xn\|SP]	01 001000 1 0 0 11111 1 11111 Rn Rt0x489FFC00 / mask 0xFFFFFC00	Store with release (half word)`release; [Rn] = Rt`Loads and stores
stlur	Wt, [Xn\|SP{, #imm9}]also shown as: stlurb, stlurh	size 011 001 00 0 imm9 00 Rn Rt0x19000000 / mask 0x3FE00C00	Store with release (unscaled, address: Rn + imm9; b = byte, h = half word)`[Rn + imm9] = Wt`Loads and stores
stlxp	Ws, Rt, Rt2, [Xn\|SP]	1 sz 001000 0 0 1 Rs 1 Rt2 Rn Rt0x88208000 / mask 0xBFE08000	Store-exclusive of a register pair with release`if the exclusive monitor is set then { release; [Rn] = Rt; [Rn + size] = Rt2; Ws = 0 } else Ws = 1`Loads and stores
stlxr	Ws, Wt, [Xn\|SP]	10 001000 0 0 0 Rs 1 11111 Rn Rt0x8800FC00 / mask 0xFFE0FC00	Store-exclusive with release (word)`if the exclusive monitor is set then { release; [Rn] = Rt; Ws = 0 } else Ws = 1`Loads and stores
stlxr	Ws, Xt, [Xn\|SP]	11 001000 0 0 0 Rs 1 11111 Rn Rt0xC800FC00 / mask 0xFFE0FC00	Store-exclusive with release (double word)`if the exclusive monitor is set then { release; [Rn] = Rt; Ws = 0 } else Ws = 1`Loads and stores
stlxrb	Ws, Wt, [Xn\|SP]	00 001000 0 0 0 Rs 1 11111 Rn Rt0x0800FC00 / mask 0xFFE0FC00	Store-exclusive with release (byte)`if the exclusive monitor is set then { release; [Rn] = Rt; Ws = 0 } else Ws = 1`Loads and stores
stlxrh	Ws, Wt, [Xn\|SP]	01 001000 0 0 0 Rs 1 11111 Rn Rt0x4800FC00 / mask 0xFFE0FC00	Store-exclusive with release (half word)`if the exclusive monitor is set then { release; [Rn] = Rt; Ws = 0 } else Ws = 1`Loads and stores
stnp	Rt, Rt2, [Xn\|SP{, #imm7}]	sf 0 101 0 000 0 imm7 Rt2 Rn Rt0x28000000 / mask 0x7FC00000	Store of a register pair with a non-temporal hint`[addr] = Rt; [addr + size] = Rt2`Loads and stores
stp	Rt, Rt2, [Xn\|SP], #imm7	sf 0 101 0 001 0 imm7 Rt2 Rn Rt0x28800000 / mask 0x7FC00000	Store of a register pair (post-indexed)`[addr] = Rt; [addr + size] = Rt2; addr = Rn; Rn = Rn + imm7 * size`Loads and stores
	Rt, Rt2, [Xn\|SP{, #imm7}]	sf 0 101 0 010 0 imm7 Rt2 Rn Rt0x29000000 / mask 0x7FC00000	Store of a register pair`[addr] = Rt; [addr + size] = Rt2; addr = Rn + imm7 * size`Loads and stores
	Rt, Rt2, [Xn\|SP, #imm7]!	sf 0 101 0 011 0 imm7 Rt2 Rn Rt0x29800000 / mask 0x7FC00000	Store of a register pair (pre-indexed)`[addr] = Rt; [addr + size] = Rt2; Rn = Rn + imm7 * size; addr = Rn`Loads and stores
	Ft, Ft2, [Xn\|SP{, #imm7}]	opc 101 1 010 0 imm7 Rt2 Rn Rt0x2D000000 / mask 0x3FC00000	Store of a pair of floating point / vector registers (opc 00 = S, 01 = D, 10 = Q)`[addr] = Ft; [addr + size] = Ft2`Loads and stores
str	Wt, [Xn\|SP{, #imm12}]	10 111 0 01 00 imm12 Rn Rt0xB9000000 / mask 0xFFC00000	Store of a word (32 bit) (address: Rn + imm12 * size)`[addr] = Wt; addr = Rn + imm12 * size`Loads and stores
	Wt, [Xn\|SP, #imm9]!	10 111 0 00 00 0 imm9 11 Rn Rt0xB8000C00 / mask 0xFFE00C00	Store of a word (32 bit) (pre-indexed: Rn is changed first)`[addr] = Wt; Rn = Rn + imm9; addr = Rn`Loads and stores
	Wt, [Xn\|SP], #imm9	10 111 0 00 00 0 imm9 01 Rn Rt0xB8000400 / mask 0xFFE00C00	Store of a word (32 bit) (post-indexed: Rn is changed afterwards)`[addr] = Wt; addr = Rn; Rn = Rn + imm9`Loads and stores
	Wt, [Xn\|SP, Rm{, extend {#amount}}]	10 111 0 00 00 1 Rm option S 10 Rn Rt0xB8200800 / mask 0xFFE00C00	Store of a word (32 bit) (address: Rn + register, extended and shifted)`[addr] = Wt; addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
	Xt, [Xn\|SP{, #imm12}]	11 111 0 01 00 imm12 Rn Rt0xF9000000 / mask 0xFFC00000	Store of a double word (64 bit) (address: Rn + imm12 * size)`[addr] = Xt; addr = Rn + imm12 * size`Loads and stores
	Xt, [Xn\|SP, #imm9]!	11 111 0 00 00 0 imm9 11 Rn Rt0xF8000C00 / mask 0xFFE00C00	Store of a double word (64 bit) (pre-indexed: Rn is changed first)`[addr] = Xt; Rn = Rn + imm9; addr = Rn`Loads and stores
	Xt, [Xn\|SP], #imm9	11 111 0 00 00 0 imm9 01 Rn Rt0xF8000400 / mask 0xFFE00C00	Store of a double word (64 bit) (post-indexed: Rn is changed afterwards)`[addr] = Xt; addr = Rn; Rn = Rn + imm9`Loads and stores
	Xt, [Xn\|SP, Rm{, extend {#amount}}]	11 111 0 00 00 1 Rm option S 10 Rn Rt0xF8200800 / mask 0xFFE00C00	Store of a double word (64 bit) (address: Rn + register, extended and shifted)`[addr] = Xt; addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
	Ft, [Xn\|SP{, #imm12}]	1 x 111 1 01 00 imm12 Rn Rt0xBD000000 / mask 0xBFC00000	Store of a single (x=0) or double (x=1) register`[Rn + imm12 * size] = Ft`Loads and stores
	Qt, [Xn\|SP{, #imm12}]	00 111 1 01 10 imm12 Rn Rt0x3D800000 / mask 0xFFC00000	Store of a 128-bit vector register`[Rn + imm12 * 16] = Qt`Loads and stores
strb	Wt, [Xn\|SP{, #imm12}]	00 111 0 01 00 imm12 Rn Rt0x39000000 / mask 0xFFC00000	Store of a byte (address: Rn + imm12 * size)`[addr] = Wt[7:0]; addr = Rn + imm12 * size`Loads and stores
	Wt, [Xn\|SP, #imm9]!	00 111 0 00 00 0 imm9 11 Rn Rt0x38000C00 / mask 0xFFE00C00	Store of a byte (pre-indexed: Rn is changed first)`[addr] = Wt[7:0]; Rn = Rn + imm9; addr = Rn`Loads and stores
	Wt, [Xn\|SP], #imm9	00 111 0 00 00 0 imm9 01 Rn Rt0x38000400 / mask 0xFFE00C00	Store of a byte (post-indexed: Rn is changed afterwards)`[addr] = Wt[7:0]; addr = Rn; Rn = Rn + imm9`Loads and stores
	Wt, [Xn\|SP, Rm{, extend {#amount}}]	00 111 0 00 00 1 Rm option S 10 Rn Rt0x38200800 / mask 0xFFE00C00	Store of a byte (address: Rn + register, extended and shifted)`[addr] = Wt[7:0]; addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
strh	Wt, [Xn\|SP{, #imm12}]	01 111 0 01 00 imm12 Rn Rt0x79000000 / mask 0xFFC00000	Store of a half word (16 bit) (address: Rn + imm12 * size)`[addr] = Wt[15:0]; addr = Rn + imm12 * size`Loads and stores
	Wt, [Xn\|SP, #imm9]!	01 111 0 00 00 0 imm9 11 Rn Rt0x78000C00 / mask 0xFFE00C00	Store of a half word (16 bit) (pre-indexed: Rn is changed first)`[addr] = Wt[15:0]; Rn = Rn + imm9; addr = Rn`Loads and stores
	Wt, [Xn\|SP], #imm9	01 111 0 00 00 0 imm9 01 Rn Rt0x78000400 / mask 0xFFE00C00	Store of a half word (16 bit) (post-indexed: Rn is changed afterwards)`[addr] = Wt[15:0]; addr = Rn; Rn = Rn + imm9`Loads and stores
	Wt, [Xn\|SP, Rm{, extend {#amount}}]	01 111 0 00 00 1 Rm option S 10 Rn Rt0x78200800 / mask 0xFFE00C00	Store of a half word (16 bit) (address: Rn + register, extended and shifted)`[addr] = Wt[15:0]; addr = Rn + extend(Rm) << (S * log2(size))`Loads and stores
sttr	Wt, [Xn\|SP{, #imm9}]also shown as: sttrb, sttrh	size 111 0 00 00 0 imm9 10 Rn Rt0x38000800 / mask 0x3FE00C00	Store with the rights of user mode (unprivileged; b = byte, h = half word)`[Rn + imm9] = Wt`Loads and stores
stur	Wt, [Xn\|SP{, #imm9}]	10 111 0 00 00 0 imm9 00 Rn Rt0xB8000000 / mask 0xFFE00C00	Store of a word (32 bit) (unscaled, address: Rn + imm9)`[addr] = Wt; addr = Rn + imm9`Loads and stores
stur	Xt, [Xn\|SP{, #imm9}]	11 111 0 00 00 0 imm9 00 Rn Rt0xF8000000 / mask 0xFFE00C00	Store of a double word (64 bit) (unscaled, address: Rn + imm9)`[addr] = Xt; addr = Rn + imm9`Loads and stores
sturb	Wt, [Xn\|SP{, #imm9}]	00 111 0 00 00 0 imm9 00 Rn Rt0x38000000 / mask 0xFFE00C00	Store of a byte (unscaled, address: Rn + imm9)`[addr] = Wt[7:0]; addr = Rn + imm9`Loads and stores
sturh	Wt, [Xn\|SP{, #imm9}]	01 111 0 00 00 0 imm9 00 Rn Rt0x78000000 / mask 0xFFE00C00	Store of a half word (16 bit) (unscaled, address: Rn + imm9)`[addr] = Wt[15:0]; addr = Rn + imm9`Loads and stores
stxp	Ws, Rt, Rt2, [Xn\|SP]	1 sz 001000 0 0 1 Rs 0 Rt2 Rn Rt0x88200000 / mask 0xBFE08000	Store-exclusive of a register pair`if the exclusive monitor is set then { [Rn] = Rt; [Rn + size] = Rt2; Ws = 0 } else Ws = 1`Loads and stores
stxr	Ws, Wt, [Xn\|SP]	10 001000 0 0 0 Rs 0 11111 Rn Rt0x88007C00 / mask 0xFFE0FC00	Store-exclusive: Ws = 0 on success (word)`if the exclusive monitor is set then { [Rn] = Rt; Ws = 0 } else Ws = 1`Loads and stores
stxr	Ws, Xt, [Xn\|SP]	11 001000 0 0 0 Rs 0 11111 Rn Rt0xC8007C00 / mask 0xFFE0FC00	Store-exclusive: Ws = 0 on success (double word)`if the exclusive monitor is set then { [Rn] = Rt; Ws = 0 } else Ws = 1`Loads and stores
stxrb	Ws, Wt, [Xn\|SP]	00 001000 0 0 0 Rs 0 11111 Rn Rt0x08007C00 / mask 0xFFE0FC00	Store-exclusive: Ws = 0 on success (byte)`if the exclusive monitor is set then { [Rn] = Rt; Ws = 0 } else Ws = 1`Loads and stores
stxrh	Ws, Wt, [Xn\|SP]	01 001000 0 0 0 Rs 0 11111 Rn Rt0x48007C00 / mask 0xFFE0FC00	Store-exclusive: Ws = 0 on success (half word)`if the exclusive monitor is set then { [Rn] = Rt; Ws = 0 } else Ws = 1`Loads and stores
stz2g	Xt\|SP, [Xn\|SP], #imm9	11011001 111 imm9 01 Rn Rt0xD9E00400 / mask 0xFFE00C00	Store of the tag and zeroing of 32 bytes (post-indexed)`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
	Xt\|SP, [Xn\|SP{, #imm9}]	11011001 111 imm9 10 Rn Rt0xD9E00800 / mask 0xFFE00C00	Store of the tag and zeroing of 32 bytes`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
	Xt\|SP, [Xn\|SP, #imm9]!	11011001 111 imm9 11 Rn Rt0xD9E00C00 / mask 0xFFE00C00	Store of the tag and zeroing of 32 bytes (pre-indexed)`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
stzg	Xt\|SP, [Xn\|SP], #imm9	11011001 011 imm9 01 Rn Rt0xD9600400 / mask 0xFFE00C00	Store of the tag and zeroing of 16 bytes (post-indexed)`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
	Xt\|SP, [Xn\|SP{, #imm9}]	11011001 011 imm9 10 Rn Rt0xD9600800 / mask 0xFFE00C00	Store of the tag and zeroing of 16 bytes`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
	Xt\|SP, [Xn\|SP, #imm9]!	11011001 011 imm9 11 Rn Rt0xD9600C00 / mask 0xFFE00C00	Store of the tag and zeroing of 16 bytes (pre-indexed)`tag of [addr] = tag of Xt (imm9 * 16 added to the address)`Memory tagging (MTE)
stzgm	Xt, [Xn\|SP]	11011001 001 000000000 00 Rn Rt0xD9200000 / mask 0xFFFFFC00	Store of several tags and zeroing of the memory (size from the system)`tags and memory of the block at Rn = Xt`Memory tagging (MTE)
sub	Rd, Rn, #imm12{, lsl #12}	sf 1 0 100010 sh imm12 Rn Rd0x51000000 / mask 0x7F800000	Subtraction of a constant (12 bit, optionally shifted left by 12)`Rd = Rn - (imm12 << (sh * 12)) (Rd and Rn may be SP)`Arithmetic
	Rd, Rn, Rm{, shift #imm6}also shown as: neg	sf 1 0 01011 shift 0 Rm imm6 Rn Rd0x4B000000 / mask 0x7F200000	Subtraction with a shifted register`Rd = Rn - shift(Rm, imm6)`Arithmetic
	Rd, Rn, Rm{, extend #imm3}	sf 1 0 01011 00 1 Rm option imm3 Rn Rd0x4B200000 / mask 0x7FE00000	Subtraction with an extended register`Rd = Rn - (extend(Rm) << imm3) (Rd and Rn may be SP)`Arithmetic
	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 10000 1 Rn Rd0x2E208400 / mask 0xBF20FC00	Subtraction of the elements`for every element: Vd[i] = Vn[i] - Vm[i]`Vector (SIMD)
subg	Xd\|SP, Xn\|SP, #uimm6, #uimm4	1 1 0 100011 0 imm6 00 imm4 Rn Rd0xD1800000 / mask 0xFFC0C000	Subtraction from an address with a change of the tag`Xd = Xn - uimm6 * 16, tag = (tag of Xn - uimm4) modulo 16`Memory tagging (MTE)
subhn	Vd.Tb, Vn.Ta, Vm.Taalso shown as: subhn2	0 Q 0 01110 size 1 Rm 0110 00 Rn Rd0x0E206000 / mask 0xBF20FC00	Subtraction with narrowing (high half; rsubhn with rounding) (signed; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = high half of (Vn[i] - Vm[i])`Vector (SIMD)
subp	Xd, Xn\|SP, Xm\|SP	1 0 0 11010110 Rm 000000 Rn Rd0x9AC00000 / mask 0xFFE0FC00	Difference of two addresses without tags (56 bit, signed)`Xd = sext(Xn[55:0]) - sext(Xm[55:0])`Memory tagging (MTE)
subps	Xd, Xn\|SP, Xm\|SP	1 0 1 11010110 Rm 000000 Rn Rd0xBAC00000 / mask 0xFFE0FC00	Difference of two addresses without tags, sets the flags`Xd = sext(Xn[55:0]) - sext(Xm[55:0])`Flags: N Z C VMemory tagging (MTE)
subs	Rd, Rn, #imm12{, lsl #12}also shown as: cmp	sf 1 1 100010 sh imm12 Rn Rd0x71000000 / mask 0x7F800000	Subtraction of a constant, sets the flags`Rd = Rn - (imm12 << (sh * 12))`Flags: N Z C VArithmetic
	Rd, Rn, Rm{, shift #imm6}also shown as: cmp, negs	sf 1 1 01011 shift 0 Rm imm6 Rn Rd0x6B000000 / mask 0x7F200000	Subtraction with a shifted register, sets the flags`Rd = Rn - shift(Rm, imm6)`Flags: N Z C VArithmetic
	Rd, Rn, Rm{, extend #imm3}also shown as: cmp	sf 1 1 01011 00 1 Rm option imm3 Rn Rd0x6B200000 / mask 0x7FE00000	Subtraction with an extended register, sets the flags`Rd = Rn - (extend(Rm) << imm3)`Flags: N Z C VArithmetic
sudot	Vd.4S, Vn.16B, Vm.4B[index]	0 Q 0 01111 00 L M Rm 1111 H 0 Rn Rd0x0F00F000 / mask 0xBFC0F400	Dot product of four bytes each with an element (Vn signed, Vm unsigned), added to the 32-bit destination`for every element: Vd[i] = Vd[i] + sum of Vn[4i+k] * Vm[index][k]`Vector (SIMD)
suqadd	Vd.T, Vn.T	0 Q 0 01110 size 10000 00011 10 Rn Rd0x0E203800 / mask 0xBF3FFC00	Addition of an unsigned value to a signed one, with saturation`for every element: Vd[i] = saturate_signed(Vd[i] + Vn[i])`Vector (SIMD)
svc	#imm16	11010100 000 imm16 000 010xD4000001 / mask 0xFFE0001F	Supervisor call to the operating system (exception level 1)`raise a supervisor call exception with imm16`System and privileged
swp	Ws, Wt, [Xn\|SP]also shown as: swpa, swpal, swpl, swpb, swpab, swpalb, swplb, swph, swpah, swpalh, swplh	size 111 0 00 A R 1 Rs 1 000 00 Rn Rt0x38208000 / mask 0x3F20FC00	Atomic exchange of a register with memory (variants: b = byte, h = half word, a = acquire, l = release)`t = [Rn]; [Rn] = Ws; Wt = t`Atomic memory operations (LSE)
sys	#op1, Cn, Cm, #op2{, Xt}also shown as: sysl, tlbi	1101010100 L 01 op1 CRn CRm op2 Rt0xD5080000 / mask 0xFFD80000	System instruction (cache, TLB and address translation operations, also written as dc, ic, at, tlbi; sysl reads a result)`execute the system operation (op1, Cn, Cm, op2) with Xt`System and privileged
tbl	Vd.T, {Vn.16B ...}, Vm.Talso shown as: tbx	0 Q 001110 00 0 Rm 0 len op 00 Rn Rd0x0E000000 / mask 0xBFE08C00	Lookup of bytes in a table of 1 to 4 vectors (tbx leaves bytes out of range unchanged, tbl sets them to 0)`for every element: Vd[i] = table[Vm[i]]`Vector (SIMD)
tbnz	Rt, #bit, label	b5 011011 1 b40 imm14 Rt0x37000000 / mask 0x7F000000	Jump if one bit of the register is 1`if bit(b5:b40) of Rt == 1 then pc = pc + sext(imm14 << 2)`Branches and calls
tbz	Rt, #bit, label	b5 011011 0 b40 imm14 Rt0x36000000 / mask 0x7F000000	Jump if one bit of the register is 0`if bit(b5:b40) of Rt == 0 then pc = pc + sext(imm14 << 2)`Branches and calls
tcancel	#imm16	11010100 011 imm16 000 000xD4600000 / mask 0xFFE0001F	Cancel of a transaction (TME)`abort the transaction with the reason imm16`System and privileged
trn1	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 0 Rm 0 010 10 Rn Rd0x0E002800 / mask 0xBF20FC00	Transposition: even-numbered elements alternately from two vectors`Vd = Vn[0], Vm[0], Vn[2], Vm[2] ...`Vector (SIMD)
trn2	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 0 Rm 0 110 10 Rn Rd0x0E006800 / mask 0xBF20FC00	Transposition: odd-numbered elements alternately from two vectors`Vd = Vn[1], Vm[1], Vn[3], Vm[3] ...`Vector (SIMD)
uaba	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 01111 1 Rn Rd0x2E207C00 / mask 0xBF20FC00	Addition of the absolute difference to the destination (unsigned)`for every element: Vd[i] = Vd[i] + abs(Vn[i] - Vm[i])`Vector (SIMD)
uabal	Vd.Tb, Vn.Ta, Vm.Taalso shown as: uabal2	0 Q 1 01110 size 1 Rm 0101 00 Rn Rd0x2E205000 / mask 0xBF20FC00	Addition of the absolute difference with widening (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vd[i] + abs(Vn[i] - Vm[i])`Vector (SIMD)
uabd	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 01110 1 Rn Rd0x2E207400 / mask 0xBF20FC00	Absolute difference (unsigned)`for every element: Vd[i] = abs(Vn[i] - Vm[i])`Vector (SIMD)
uabdl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: uabdl2	0 Q 1 01110 size 1 Rm 0111 00 Rn Rd0x2E207000 / mask 0xBF20FC00	Absolute difference with widening (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = abs(Vn[i] - Vm[i]) (wide result)`Vector (SIMD)
uadalp	Vd.T, Vn.T	0 Q 1 01110 size 10000 00110 10 Rn Rd0x2E206800 / mask 0xBF3FFC00	Pairwise addition with widening, added to the destination (unsigned)`for every element: Vd[i] = Vd[i] + Vn[2i] + Vn[2i+1]`Vector (SIMD)
uaddl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: uaddl2	0 Q 1 01110 size 1 Rm 0000 00 Rn Rd0x2E200000 / mask 0xBF20FC00	Addition with widening (both operands become twice as wide) (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] + Vm[i] (wide result)`Vector (SIMD)
uaddlp	Vd.T, Vn.T	0 Q 1 01110 size 10000 00010 10 Rn Rd0x2E202800 / mask 0xBF3FFC00	Pairwise addition of adjacent elements with widening (unsigned)`for every element: Vd[i] = Vn[2i] + Vn[2i+1]`Vector (SIMD)
uaddlv	Vd, Vn.T	0 Q 1 01110 size 11000 00011 10 Rn Rd0x2E303800 / mask 0xBF3FFC00	Sum of all elements with widening (unsigned)`Vd = sum of all elements of Vn`Vector (SIMD)
uaddw	Vd.Tb, Vn.Ta, Vm.Taalso shown as: uaddw2	0 Q 1 01110 size 1 Rm 0001 00 Rn Rd0x2E201000 / mask 0xBF20FC00	Addition of a wide and a narrow operand (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] + Vm[i] (Vn is wide)`Vector (SIMD)
ubfm	Rd, Rn, #immr, #immsalso shown as: lsl, lsr, ubfiz, ubfx, uxtb, uxth	sf 1 0 100110 N immr imms Rn Rd0x53000000 / mask 0x7F800000	Bitfield move with zeros (base form of lsl, lsr, ubfx, uxtb ...)`Rd = zero-extended field of Rn selected by immr, imms`Bitfields
ucvtf	Fd, Rn	sf 0 0 11110 ftype 1 00 011 000000 Rn Rd0x1E230000 / mask 0x7F3FFC00	Conversion of an unsigned integer to floating point`Fd = (float) zext(Rn)`Floating point (scalar)
ucvtf	Vd.T, Vn.T	0 Q 1 01110 0 sz 10000 11101 10 Rn Rd0x2E21D800 / mask 0xBFBFFC00	Conversion of an unsigned integer to floating point`for every element: Vd[i] = (float) Vn[i]`Vector (SIMD)
udf	#imm16	0000000000000000 imm160x00000000 / mask 0xFFFF0000	Permanently undefined instruction (always raises an exception)`raise undefined-instruction exception`System and privileged
udiv	Rd, Rn, Rm	sf 0 0 11010110 Rm 000010 Rn Rd0x1AC00800 / mask 0x7FE0FC00	Unsigned division (division by 0 gives 0)`Rd = Rn / Rm`Arithmetic
udot	Vd.4S, Vn.16B, Vm.16B	0 Q 1 01110 10 0 Rm 10010 1 Rn Rd0x2E809400 / mask 0xBFE0FC00	Dot product of four bytes each (unsigned), added to the 32-bit destination`for every element: Vd[i] = Vd[i] + sum of Vn[4i+k] * Vm[4i+k]`Vector (SIMD)
uhadd	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 00000 1 Rn Rd0x2E200400 / mask 0xBF20FC00	Halving addition (unsigned)`for every element: Vd[i] = (Vn[i] + Vm[i]) >> 1`Vector (SIMD)
uhsub	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 00100 1 Rn Rd0x2E202400 / mask 0xBF20FC00	Halving subtraction (unsigned)`for every element: Vd[i] = (Vn[i] - Vm[i]) >> 1`Vector (SIMD)
umaddl	Xd, Wn, Wm, Xaalso shown as: umull	1 00 11011 101 Rm 0 Ra Rn Rd0x9BA00000 / mask 0xFFE08000	Unsigned multiply 32 x 32 bit, added to 64 bit`Xd = Xa + zext(Wn) * zext(Wm)`Arithmetic
umax	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 01100 1 Rn Rd0x2E206400 / mask 0xBF20FC00	Maximum of the elements (unsigned)`for every element: Vd[i] = max_unsigned(Vn[i], Vm[i])`Vector (SIMD)
umaxp	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 10100 1 Rn Rd0x2E20A400 / mask 0xBF20FC00	Maximum of adjacent element pairs (unsigned)`for every element: Vd[i] = max_unsigned of each pair of (Vn:Vm)`Vector (SIMD)
umaxv	Vd, Vn.T	0 Q 1 01110 size 11000 01010 10 Rn Rd0x2E30A800 / mask 0xBF3FFC00	Maximum of all elements (unsigned)`Vd = max_unsigned of all elements of Vn`Vector (SIMD)
umin	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 01101 1 Rn Rd0x2E206C00 / mask 0xBF20FC00	Minimum of the elements (unsigned)`for every element: Vd[i] = min_unsigned(Vn[i], Vm[i])`Vector (SIMD)
uminp	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 10101 1 Rn Rd0x2E20AC00 / mask 0xBF20FC00	Minimum of adjacent element pairs (unsigned)`for every element: Vd[i] = min_unsigned of each pair of (Vn:Vm)`Vector (SIMD)
uminv	Vd, Vn.T	0 Q 1 01110 size 11000 11010 10 Rn Rd0x2E31A800 / mask 0xBF3FFC00	Minimum of all elements (unsigned)`Vd = min_unsigned of all elements of Vn`Vector (SIMD)
umlal	Vd.Tb, Vn.Ta, Vm.Taalso shown as: umlal2	0 Q 1 01110 size 1 Rm 1000 00 Rn Rd0x2E208000 / mask 0xBF20FC00	Multiplication with widening, added to the destination (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vd[i] + Vn[i] * Vm[i]`Vector (SIMD)
umlal	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: umlal2	0 Q 1 01111 size L M Rm 0010 H 0 Rn Rd0x2F002000 / mask 0xBF00F400	Multiplication by an element with widening, added to the destination (unsigned) (Q = 1: name with 2)`for every element: Vd[i] = Vd[i] + Vn[i] * Vm[index]`Vector (SIMD)
umlsl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: umlsl2	0 Q 1 01110 size 1 Rm 1010 00 Rn Rd0x2E20A000 / mask 0xBF20FC00	Multiplication with widening, subtracted from the destination (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vd[i] - Vn[i] * Vm[i]`Vector (SIMD)
umlsl	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: umlsl2	0 Q 1 01111 size L M Rm 0110 H 0 Rn Rd0x2F006000 / mask 0xBF00F400	Multiplication by an element with widening, subtracted from the destination (unsigned) (Q = 1: name with 2)`for every element: Vd[i] = Vd[i] - Vn[i] * Vm[index]`Vector (SIMD)
ummla	Vd.4S, Vn.16B, Vm.16B	0 1 1 01110 10 0 Rm 10100 1 Rn Rd0x6E80A400 / mask 0xFFE0FC00	Matrix multiplication 2x8 times 8x2 (unsigned), added to the destination`Vd(2x2) = Vd(2x2) + Vn(2x8) * Vm(8x2)`Vector (SIMD)
umov	Rd, Vn.Ts[index]also shown as: mov	0 Q 0 01110000 imm5 0 0111 1 Rn Rd0x0E003C00 / mask 0xBFE0FC00	Copy of an element into an integer register (unsigned)`Rd = zext(Vn[index])`Vector (SIMD)
umsubl	Xd, Wn, Wm, Xaalso shown as: umnegl	1 00 11011 101 Rm 1 Ra Rn Rd0x9BA08000 / mask 0xFFE08000	Unsigned multiply 32 x 32 bit, subtracted from 64 bit`Xd = Xa - zext(Wn) * zext(Wm)`Arithmetic
umulh	Xd, Xn, Xm	1 00 11011 110 Rm 0 11111 Rn Rd0x9BC07C00 / mask 0xFFE0FC00	Unsigned multiply, the high 64 bits of the result`Xd = (zext(Xn) * zext(Xm)) >> 64`Arithmetic
umull	Vd.Tb, Vn.Ta, Vm.Taalso shown as: umull2	0 Q 1 01110 size 1 Rm 1100 00 Rn Rd0x2E20C000 / mask 0xBF20FC00	Multiplication with widening (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] * Vm[i] (wide result)`Vector (SIMD)
umull	Vd.Ta, Vn.Tb, Vm.Ts[index]also shown as: umull2	0 Q 1 01111 size L M Rm 1010 H 0 Rn Rd0x2F00A000 / mask 0xBF00F400	Multiplication by an element with widening (unsigned) (Q = 1: name with 2)`for every element: Vd[i] = Vn[i] * Vm[index]`Vector (SIMD)
uqadd	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 00001 1 Rn Rd0x2E200C00 / mask 0xBF20FC00	Addition with saturation (unsigned)`for every element: Vd[i] = saturate_unsigned(Vn[i] + Vm[i])`Vector (SIMD)
uqrshl	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 01011 1 Rn Rd0x2E205C00 / mask 0xBF20FC00	Shift per element with rounding and saturation (unsigned)`for every element: Vd[i] = saturate_unsigned(round(Vn[i] << Vm[i]))`Vector (SIMD)
uqrshrn	Vd.Tb, Vn.Ta, #shiftalso shown as: uqrshrn2	0 Q 1 011110 0 immh immb 10011 1 Rn Rd0x2F009C00 / mask 0xBFC0FC00	Shift right with narrowing, rounding and saturation (unsigned) (Q = 1: name with 2)`for every element: Vd[i] = saturate_unsigned(round(Vn[i] >> shift))`Vector (SIMD)
uqshl	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 01001 1 Rn Rd0x2E204C00 / mask 0xBF20FC00	Shift per element with saturation (unsigned)`for every element: Vd[i] = saturate_unsigned(Vn[i] << Vm[i])`Vector (SIMD)
uqshl	Vd.T, Vn.T, #shift	0 Q 1 011110 immh immb 01110 1 Rn Rd0x2F007400 / mask 0xBF80FC00	Shift left with saturation (unsigned)`for every element: Vd[i] = saturate_unsigned(Vn[i] << shift)`Vector (SIMD)
uqshrn	Vd.Tb, Vn.Ta, #shiftalso shown as: uqshrn2	0 Q 1 011110 0 immh immb 10010 1 Rn Rd0x2F009400 / mask 0xBFC0FC00	Shift right with narrowing and saturation (unsigned) (Q = 1: name with 2)`for every element: Vd[i] = saturate_unsigned(Vn[i] >> shift)`Vector (SIMD)
uqsub	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 00101 1 Rn Rd0x2E202C00 / mask 0xBF20FC00	Subtraction with saturation (unsigned)`for every element: Vd[i] = saturate_unsigned(Vn[i] - Vm[i])`Vector (SIMD)
uqxtn	Vd.T, Vn.Talso shown as: uqxtn2	0 Q 1 01110 size 10000 10100 10 Rn Rd0x2E214800 / mask 0xBF3FFC00	Narrowing with saturation (unsigned)`for every element: Vd[i] = saturate_unsigned(Vn[i])`Vector (SIMD)
urhadd	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 00010 1 Rn Rd0x2E201400 / mask 0xBF20FC00	Halving addition with rounding (unsigned)`for every element: Vd[i] = (Vn[i] + Vm[i] + 1) >> 1`Vector (SIMD)
urshl	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 01010 1 Rn Rd0x2E205400 / mask 0xBF20FC00	Shift per element with rounding (unsigned)`for every element: Vd[i] = round(Vn[i] << Vm[i])`Vector (SIMD)
urshr	Vd.T, Vn.T, #shift	0 Q 1 011110 immh immb 00100 1 Rn Rd0x2F002400 / mask 0xBF80FC00	Shift right with rounding (unsigned)`for every element: Vd[i] = round(Vn[i] >> shift)`Vector (SIMD)
ursra	Vd.T, Vn.T, #shift	0 Q 1 011110 immh immb 00110 1 Rn Rd0x2F003400 / mask 0xBF80FC00	Shift right with rounding and addition to the destination (unsigned)`for every element: Vd[i] = Vd[i] + round(Vn[i] >> shift)`Vector (SIMD)
usdot	Vd.4S, Vn.16B, Vm.16B	0 Q 0 01110 10 0 Rm 10011 1 Rn Rd0x0E809C00 / mask 0xBFE0FC00	Dot product of four bytes each (Vn unsigned, Vm signed), added to the 32-bit destination`for every element: Vd[i] = Vd[i] + sum of Vn[4i+k] * Vm[4i+k]`Vector (SIMD)
ushl	Vd.T, Vn.T, Vm.T	0 Q 1 01110 size 1 Rm 01000 1 Rn Rd0x2E204400 / mask 0xBF20FC00	Shift left or right per element (unsigned)`for every element: Vd[i] = Vn[i] << Vm[i] (a negative count shifts right)`Vector (SIMD)
ushll	Vd.Ta, Vn.Tb, #shiftalso shown as: ushll2, uxtl, uxtl2	0 Q 1 011110 0 immh immb 10100 1 Rn Rd0x2F00A400 / mask 0xBFC0FC00	Widening with a left shift (unsigned; uxtl is a shift by 0)`for every element: Vd[i] = zext(Vn[i]) << shift`Vector (SIMD)
ushr	Vd.T, Vn.T, #shift	0 Q 1 011110 immh immb 00000 1 Rn Rd0x2F000400 / mask 0xBF80FC00	Shift right, signed (arithmetic) (unsigned)`for every element: Vd[i] = Vn[i] >> shift`Vector (SIMD)
usmmla	Vd.4S, Vn.16B, Vm.16B	0 1 0 01110 10 0 Rm 10101 1 Rn Rd0x4E80AC00 / mask 0xFFE0FC00	Matrix multiplication 2x8 times 8x2 (Vn unsigned, Vm signed), added to the destination`Vd(2x2) = Vd(2x2) + Vn(2x8) * Vm(8x2)`Vector (SIMD)
usqadd	Vd.T, Vn.T	0 Q 1 01110 size 10000 00011 10 Rn Rd0x2E203800 / mask 0xBF3FFC00	Addition of a signed value to an unsigned one, with saturation`for every element: Vd[i] = saturate_unsigned(Vd[i] + Vn[i])`Vector (SIMD)
usra	Vd.T, Vn.T, #shift	0 Q 1 011110 immh immb 00010 1 Rn Rd0x2F001400 / mask 0xBF80FC00	Shift right and addition to the destination (unsigned)`for every element: Vd[i] = Vd[i] + (Vn[i] >> shift)`Vector (SIMD)
usubl	Vd.Tb, Vn.Ta, Vm.Taalso shown as: usubl2	0 Q 1 01110 size 1 Rm 0010 00 Rn Rd0x2E202000 / mask 0xBF20FC00	Subtraction with widening (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] - Vm[i] (wide result)`Vector (SIMD)
usubw	Vd.Tb, Vn.Ta, Vm.Taalso shown as: usubw2	0 Q 1 01110 size 1 Rm 0011 00 Rn Rd0x2E203000 / mask 0xBF20FC00	Subtraction of a narrow operand from a wide one (unsigned; Q = 1: high half of the sources, name with 2)`for every element: Vd[i] = Vn[i] - Vm[i] (Vn is wide)`Vector (SIMD)
uzp1	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 0 Rm 0 001 10 Rn Rd0x0E001800 / mask 0xBF20FC00	Extraction of the even-numbered elements of two vectors`Vd = even elements of (Vn:Vm)`Vector (SIMD)
uzp2	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 0 Rm 0 101 10 Rn Rd0x0E005800 / mask 0xBF20FC00	Extraction of the odd-numbered elements of two vectors`Vd = odd elements of (Vn:Vm)`Vector (SIMD)
xar	Vd.2D, Vn.2D, Vm.2D, #imm6	11001110 100 Rm imm6 Rn Rd0xCE800000 / mask 0xFFE00000	Exclusive OR and rotation to the right (SHA-3)`Vd = rotate_right(Vn ^ Vm, imm6)`Cryptography
xtn	Vd.T, Vn.Talso shown as: xtn2	0 Q 0 01110 size 10000 10010 10 Rn Rd0x0E212800 / mask 0xBF3FFC00	Narrowing of the elements (the high half is cut off)`for every element: Vd[i] = low half of Vn[i]`Vector (SIMD)
zip1	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 0 Rm 0 011 10 Rn Rd0x0E003800 / mask 0xBF20FC00	Interleaving of the low halves of two vectors, alternately`Vd = Vn[0], Vm[0], Vn[1], Vm[1] ...`Vector (SIMD)
zip2	Vd.T, Vn.T, Vm.T	0 Q 0 01110 size 0 Rm 0 111 10 Rn Rd0x0E007800 / mask 0xBF20FC00	Interleaving of the high halves of two vectors, alternately`Vd = Vn[n/2], Vm[n/2], Vn[n/2+1] ...`Vector (SIMD)